Si5351B-A-GU Silicon Laboratories Inc, Si5351B-A-GU Datasheet - Page 30

• Manufacturer Part Number: Si5351B-A-GU
• Description: Clock Generators & Support Products AnyRate 2 PLL 125MHz Clk w/VCXO&I2C 8out
• Manufacturer: Silicon Laboratories Inc
• Type: Any Frequency CMOS Clock Generatorr

Specifications of Si5351B-A-GU

• Mounting Style: SMD/SMT
• Max Input Freq: 0.008 MHz
• Max Output Freq: 133 MHz
• Number Of Outputs: 8
• Operating Supply Voltage: 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 25 mA
• Package / Case: QSOP-24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5351A/B/C
Reset value = 0000 0000
30
Register 16. CLK0 Control
Name
Bit
3:2
1:0
Type
7
6
5
4
Bit
CLK0_IDRV[1:0] CLK0 Output Rise and Fall time / Drive Strength Control.
CLK0_SRC[1:0] Output Clock 0 Input Source.
CLK0_PDN
CLK0_PDN
MS0_SRC
CLK0_INV
MS0_INT
Name
R/W
D7
MS0_INT
Clock 0 Power Down.
This bit allows powering down the CLK0 output driver to conserve power when the out-
put is unused.
0: CLK0 is powered up.
1: CLK0 is powered down.
MultiSynth 0 Integer Mode.
This bit can be used to force MS0 into Integer mode to improve jitter performance. Note
that the fractional mode is necessary when a delay offset is specified for CLK0.
0: MS0 operates in fractional division mode.
1: MS0 operates in integer mode.
MultiSynth Source Select for CLK0.
0: Select PLLA as the source for MultiSynth0.
1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0.
Output Clock 0 Invert.
0: Output Clock 0 is not inverted.
1: Output Clock 0 is inverted.
These bits determine the input source for CLK0.
00: Select the XTAL as the clock source for CLK0. This option by-passes both synthesis
stages (PLL/VCXO & MultiSynth) and connects CLK0 directly to the oscillator which
generates an output frequency determined by the XTAL frequency.
01: Select CLKIN as the clock source for CLK0. This by-passes both synthesis stages
(PLL/VCXO & MultiSynth) and connects CLK0 directly to the CLKIN input. This essen-
tially creates a buffered output of the CLKIN input.
10: Reserved. Do not select this option.
11: Select MultiSynth 0 as the source for CLK0. Select this option when using the
Si5351 to generate free-running or synchronous clocks.
00: 2 mA
01: 4 mA
10: 6 mA
11: 8 mA
R/W
D6
MS0_SRC
R/W
D5
Preliminary Rev. 0.95
CLK0_INV
R/W
D4
Function
CLK0_SRC[1:0]
D3
R/W
D2
CLK0_IDRV[1:0]
D1
R/W
D0