CY28RS480ZXC Silicon Laboratories Inc, CY28RS480ZXC Datasheet - Page 4

• Manufacturer Part Number: CY28RS480ZXC
• Description: Clock Generators & Support Products ATIR RS480 Chipset System Clock
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28RS480ZXC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 22, 2006
Table 3. Byte Read and Byte Write Protocol (continued)
Control Registers
Byte 0:Control Register 0
Byte 1: Control Register 1
27:20
18:11
Bit
Bit
Bit
19
28
29
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
@Pup
@Pup
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Byte Write Protocol
Description
SRCS[T/C]1
SRCS[T/C]0
RESERVED
SRC [T/C]0
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
CPU[T/C]1
CPU[T/C]0
USB_48
Name
Name
REF2
REF1
REF0
PCI0
SRC[T/C]5 Output Enable
SRC[T/C]4 Output Enable
SRC[T/C]3 Output Enable
SRC[T/C]2 Output Enable
SRC[T/C]1 Output Enable
SRC[T/C]0 Output Enable
RESERVED
CPU[T/C]1 Output Enable
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
0 = Disable (Hi-Z), 1 = Enable
0 = Disable (Hi-Z), 1 = Enable
0 = Disable (Hi-Z), 1 = Enable
0 = Disable (Hi-Z), 1 = Enable
0 = Disable (Hi-Z), 1 = Enable
SRCS[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRCS[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
REF2 Output Enable
0 = Disable, 1 = Enable
REF1 Output Enable
0 = Disable, 1 = Enable
REF0 Output Enable
0 = Disable, 1 = Enable
PCI0 Output Enable
0 = Disable, 1 = Enable
USB_48MHz Output Enable
0 = Disable, 1 = Enable
0 = Disable (Hi-Z), 1 = Enable
0 = Disable (Hi-Z), 1 = Enable
27:21
18:11
37:30
Bit
19
20
28
29
38
39
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Description
Description
Byte Read Protocol
Description
CY28RS480
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