SL28506BZI Silicon Laboratories Inc, SL28506BZI Datasheet
SL28506BZI
Specifications of SL28506BZI
Related parts for SL28506BZI
SL28506BZI Summary of contents
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Features ® • Compliant to Intel CK505 • Selectable CPU frequencies • SRC clocks compliant to PCI-Express Gen2 (except SRC0 and SRC1) • Differential CPU clock pairs • 100 MHz Differential SRC clocks • 100 MHz Differential LCD clock • ...
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Pin Definitions Pin No. Name 1 PCI_0/OE#_0/2_A 2 VDD_PCI 3 PCI_1/OE#_1/4_A 4 PCI_2/TME 5 PCI_3/CFG0 6 PCI_4/SRC5_SEL 7 PCIF_0/ITP_EN 8 VSS_PCI 9 VDD_48 10 USB_48/FSA 11 VSS_48 12 VDD_IO 13 SRC0/DOT96T 14 SRC0#/DOT96# 15 VSS_IO 16 VDD_PLL3 17 SRC1/LCD_100/SE1 18 ...
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Pin Definitions (continued) Pin No. Name 31 SRC9# 32 SRC11#/OE#_9 33 SRC11/OE#_10 34 SRC10 35 SRC#10 36 VDD_SRC_IO 37 SRC5#CPU_STOP# 38 SRC5/PCI_STOP# 39 VDD_SRC 40 SRC6# 41 SRC6 42 VSS_SRC 43 SRC7#/OE#_6 44 SRC7/OE#_8 45 VDD_SRC_IO 46 SRC8#/CPUC2_ITP# 47 SRC8/CPUT2_ITP ...
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Pin Definitions (continued) Pin No. Name 59 XOUT 60 XIN 61 VDD_REF 62 REF0/FSC/TEST_SEL 63 SMB_DATA 64 SMB_CLK Rev 1.3 August 4, 2008 Type O, SE 14.318 MHz Crystal output. I 14.318 MHz Crystal input. PWR 3.3V Power supply for ...
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Frequency Select Pin (FSA, FSB, and FSC) To achieve host clock frequency selection, apply the appro- priate logic levels to FS_A, FS_B, and FS_C, inputs before CK_PWRGD assertion (as seen by the clock synthesizer). When CK_PWRGD is sampled HIGH by ...
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Table 3. Block Read and Block Write Protocol Block Write Protocol Bit Description 1 Start 8:2 Slave address–7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code–8 bits 19 Acknowledge from slave 27:20 Byte Count–8 bits 2 (Skip this ...
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Byte 0: Control Register FS_C 6 HW FS_B 5 HW FS_A 4 0 iAMT_EN 3 0 RESERVED 2 0 SRC_MAIN_SEL 1 0 SATA_SEL 0 1 PD_Restore Byte 1: Control Register 1 Bit @Pup Name 7 0 SRC0_SEL ...
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Byte 2: Control Register 2 (continued) Bit @Pup Name 3 1 PCI3_OE 2 1 PCI2_OE 1 1 PCI1_OE 0 1 PCI0_OE Byte 3: Control Register 3 Bit @Pup Name 7 1 SRC11_OE 6 1 SRC10_OE 5 1 SRC9_OE 4 1 ...
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Byte 5: Control Register 5 (continued) Bit @Pup Name 0 0 OE#_1/4_SEL_B Byte 6: Control Register 6 Bit @Pup Name 7 0 OE#_6_EN 6 0 OE#_8_EN 5 0 OE#_9_EN 4 0 OE#_10_EN 3 0 RESERVED 2 0 RESERVED 1 0 ...
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Byte 9 Control Register 9 Bit @Pup Name 7 0 PCIF0_STP_CTRL 6 HW_Pin TME_STRAP 5 1 REF_Bit1 4 0 TEST_MODE_SEL 3 0 TEST_MODE_ENTRY 2 1 IO_VOUT2 1 0 IO_VOUT1 0 1 IO_VOUT0 Byte 10 Control Register 10 Bit @Pup Name ...
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Byte 11 Control Register 25MHz_EN_SE1 4 1 RESERVED 3 0 CPU2_AMT_EN 2 1 CPU1_AMT_EN 1 HW PCI-E_GEN2 0 1 CPU2_STP_CRTL Byte 12 Byte Count Bit @Pup Name 7 0 RESERVED 6 0 RESERVED 5 0 BC5 4 ...
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Byte 13 Control Register SW_PCI Byte 14 Control Register 14 Bit @Pup Name 7 0 CPU_DAF_N7 6 0 CPU_DAF_N6 5 0 CPU_DAF_N5 4 0 CPU_DAF_N4 3 0 CPU_DAF_N3 2 0 CPU_DAF_N2 1 0 CPU_DAF_N1 0 0 CPU_DAF_N0 ...
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Byte 17 Control Register Prog_PCI-E_EN 3 0 Prog_CPU_EN 2 0 RESERVED 1 0 RESERVED 0 0 RESERVED Byte 18 Control Register 18 Bit @Pup Name 7 0 PCIF/PCI_Bit2 6 1 PCIF/PCI_Bit0 5 0 USB_Bit2 4 0 USB_Bit0 ...
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C lock C hip Ci2 Ci1 X2 X1 Cs1 XTAL Ce1 Ce2 Figure 2. Crystal Loading Example Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side ...
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PD Assertion When PS is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must held LOW. In the event that PD mode is desired ...
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Figure 4. CPU_STP# Assertion Waveform CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation ...
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CPU_STOP# PD# CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state PCI_STP# Assertion The PCI_STP# signal is an active LOW input used to synchro- nously stop and start the PCI outputs while ...
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Table 6. Output Driver Status during PCI-STOP# and CPU-STOP# Single-ended Clocks Stoppable Non Stoppable Differential Clocks Stoppable Non Stoppable Table 7. Output Driver Status All Single-ended Clocks w/o Strap w/Strap Latches Open State Low Hi-Z Powerdown Low Hi-Z M1 ...
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Figure 8. Clock Generator Power-up/Run State Diagram Rev 1.3 August 4, 2008 SL28506 Page ...
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Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V IO Supply Voltage DD_IO V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J Ø Dissipation, Junction ...
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AC Electrical Specifications Parameter Description Crystal T XIN Duty Cycle DC T XIN Period PERIOD T /T XIN Rise and Fall Times XIN Cycle to Cycle Jitter CCJ L Long-term Accuracy ACC CPU at 0.7V T CPUT ...
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AC Electrical Specifications (continued) Parameter Description T /T CPUT and CPUC Rise and Fall Time Rise/Fall Matching RFM V Voltage High HIGH V Voltage Low LOW V Crossing Point Voltage at 0.7V Swing OX SRC T SRCT ...
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AC Electrical Specifications (continued) Parameter Description V Crossing Point Voltage at 0.7V Swing OX PCI/PCIF T PCI Duty Cycle DC T Spread Disabled PCIF/PCI Period PERIOD T Spread Enabled PCIF/PCI Period, SSC PERIODSS T Spread Disabled PCIF/PCI Period PERIODAbs T ...
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AC Electrical Specifications Parameter Description T /T Rising and Falling Edge Rate Cycle to Cycle Jitter CCJ L 98M Long Term Accuracy ACC REF T REF Duty Cycle DC T REF Period PERIOD T REF Absolute Period ...
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Figure 11. Single-ended Output Signals (for AC Parameters Measurement) Rev 1.3 August 4, 2008 SL28506 Page ...
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For CPU, SRC, and DOT96 Signals and Reference The following diagram shows the test load configuration for the differential CPU and SRC outputs. OUT+ OUT- Figure 13. Differential Measurement for Differential Output Signals (for AC Parameters Measuremement Figure 14. Single-ended ...
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Ordering Information Part Number Lead-free SL28506BZC 64-pin TSSOP SL28506BZCT 64-pin TSSOP–Tape and Reel SL 28 506 yyy T Package Diagram 64-Lead Thin Shrunk Small Outline Package ( mm) Z64 32 33 16.90[0.665] 17.10[0.673] 0.50[0.020] ...
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Document History Page Document Title: SL28506 Clock Generator for Intel Eaglelake Chipset Orig. of REV. Issue Date Change 1.0 7/12/07 JMA New datasheet 1.1 10/30/07 JMA 1. Changed -1% spread to -0.45% spread in Byte 13 Bit 5 2. Added ...