SL18860DC Silicon Laboratories Inc, SL18860DC Datasheet
SL18860DC
Manufacturer Part Number
SL18860DC
Description
Clock Buffer Lo phase jitter TCXO distribution buffer
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SL18860DC.pdf
(12 pages)
Specifications of SL18860DC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Key Features
Application
Block Diagram
Rev 1.7, December 16 , 2010
2400 West Cesar Chavez, Austin, TX 78701
• Low current consumption
• 1.7V to 3.65V power supply operation
• 10MHz to 52MHz CLKIN
• Supports LVCMOS and sine inputs
• Suports 3 single-ended LVCMOS square or clipped
• OE1/2/3 functions for each CLKOUT1/2/3 outputs
• OE_OSC control pin to enable external TCXO/XO
• Ultra-Low phase noise
• Ultra low standby current
• 10-pin TDFN package (1.4x2.0x0.75 mm)
• Industrial -40 ºC to 85 ºC temperature range
• Smart Mobile Handsets
• Multi-mode RF Clock Distribution
• Baseband Peripheral Clock Distribution
sine wave outputs
- 2.7mA-typ (VDD=1.8V and CL=0)
OE_OSC
CLKIN
3
4
OE1
6
CONTROL LOGIC
1+(512) 416-8500
3-Channel Clock Distribution Buffer
OE2
7
OE3
5
Description
The SL18860DC product is a high performance 3 output
clock distribution buffer and provides 3 outputs from a
single input clock by using SLI proprietary low phase
noise and low power dissipation circuit design.
The SL18860DC can be used in baseband mobile RF
applications including WLAN, Bluetooth and DVB-H as an
input clock reference. The product designed to isolate
each device driven by their clock outputs to minimize
interference between these devices.
Each of the clock buffer outputs can be individually
disabled by using OE1/2/3 control pins to reduce the
power consumption if the connected device does not need
the clock. The device operates from single power supply
from 1.7V to 3.65V and from -40 ºC to 85 ºC.
Benefits
• Fast Time-to-market
• Cost Reduction
• Low Power Dissipation
• Low Phase Noise
VDD
1+(512) 416-9669
2
VSS
1
10
8
9
SL18860DC
CLKOUT3
CLKOUT1
CLKOUT2
www.silabs.com
Page 1 of 12
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