PI6C185-00QIE Pericom Semiconductor, PI6C185-00QIE Datasheet - Page 5

• Manufacturer Part Number: PI6C185-00QIE
• Description: Clock Buffer Precision 1:7 Clock Driver
• Manufacturer: Pericom Semiconductor

Specifications of PI6C185-00QIE

• Number Of Outputs: 7
• Max Input Freq: 125 MHz
• Propagation Delay (max): 5 ns
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Minimum and Maximum Expected Capacitive Loads
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Design Guidelines to Reduce EMI
1. Place series R
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock
4. Position clock signals away from signals that go to any cables or any external connectors.
S
C
D
Testing is done with an additional 500-ohm resistor in parallel.
for CI is 10pF. R
are still within the specified values.
traces from plane to plane (refer to rule #2).
o l
R
A
k c
M
08-0298
M
. n i
0 2
S
L
resistors and CI capacitors as close as possible to the respective clock pins. Typical value
a o
S
Series resistor value can be increased to reduce EMI provided that the rise and fall time
d
Waveform
M
a
. x
Waveform
Interface
Input
Clocking
0 3
L
(TTL)
a o
3.3V
Output
d
U
2.4
1.5
0.4
p
n
F
s t i
t
plh
S
t
SDRISE
D
S
R
e p
1.5V
A
Figure 1. Clock Waveforms
N
i c
M
t o
c i f
s e
tSDKH
I D
i t a
Output
Buffer
M
n o
1.5V
M
tSDKP
5
t
SDFALL
Test Load
tSDKL
Test
Point
1.5V
1.5V
t
phl
Precision 1-7 Clock Buffer
PS8317F
PI6C185-00
11/13/08