DS26503LN Maxim Integrated Products, DS26503LN Datasheet - Page 80

• Manufacturer Part Number: DS26503LN
• Description: Timers & Support Products E1-T1-J1 BITS Elemen t T1-E1-J1 BITS Elem
• Manufacturer: Maxim Integrated Products
• Type: Clock Recoveryr

Specifications of DS26503LN

• Supply Voltage (max): 3.46 V
• Supply Voltage (min): 3.13 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 85 mA
• Package / Case: LQFP-64

The transmit line drive has two modes of operation: fixed gain or automatic gain. In the fixed gain mode,
the transmitter outputs a fixed current into the network load to achieve a nominal pulse amplitude. In the
automatic gain mode, the transmitter adjusts its output level to compensate for slight variances in the
network load. See the Transmit Line Build-Out Control (TLBC) register for details.
13.3.1 Transmit Short-Circuit Detector/Limiter
The DS26503 has an automatic short-circuit limiter that limits the source current to approximately 50mA
(rms) on the network side of the transformer in E1 modes of operations and 70mA (rms) on the network
side of the transformer in T1 modes of operation. These values are approximate and are not guaranteed by
production testing. This feature can be disabled by setting the SCLD bit (LIC2.1) = 1. TCLE (SR1.2)
provides a real-time indication of when the current limiter is activated. If the current limiter is disabled,
TCLE will indicate that a short-circuit condition exist. Status Register SR1.2 provides a latched version
of the information, which can be used to activate an interrupt when enable via the IMR1 register. When
set low, the TPD bit (LIC1.0) will power-down the transmit line driver and tri-state the TTIP and TRING
pins.
13.3.2 Transmit Open-Circuit Detector
The DS26503 can also detect when the TTIP or TRING outputs are open circuited. TOCD (SR1.1) will
provide a real-time indication of when an open circuit is detected. SR1 provides a latched version of the
information (SR1.1), which can be used to activate an interrupt when enable via the IMR1 register. The
functionality of these bits is not guaranteed by production testing.
13.3.3 Transmit BPV Error Insertion
When IBPV (LIC2.5) is transitioned from a zero to a one, the device waits for the next occurrence of
three consecutive ones to insert a BPV. IBPV must be cleared and set again for another BPV error
insertion.
13.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode)
The DS26503 can transmit the 2.048MHz square-wave synchronization clock. To transmit the 2.048MHz
clock, when in E1 mode, set the mode configuration bits in the Mode Configuration Register (MCREG).
13.4 MCLK Pre-Scaler
A 2.048MHz x 2
interface mode only) clock must be applied to MCLK. A pre-scaler (divide by 2, 4, or 8) and PLLs are
selected to product an internal 2.048MHz or 1.544MHz clock. ITU specification G.703 requires an accuracy
of ±50ppm for both T1 and E1. TR62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces.
A pre-scaler divides the 16.384MHz, 12.8MHz, 8.192MHz, or 4.096MHz clock down to 2.048MHz. An on-
board PLL for the jitter attenuator converts the 2.048MHz clock to a 1.544MHz rate for T1 applications.
Setting JACKS0 (LIC2.3) to logic 0 bypasses this PLL.
13.5 Jitter Attenuator
The DS26503’s jitter attenuator can be set to a depth of either 32 bits or 128 bits via the JABDS bit
(LIC1.2). The 128-bit mode is used in applications where large excursions of wander are expected. The
32-bit mode is used in delay-sensitive applications. The characteristics of the attenuation are shown in
Figure 13-10
transmit path by appropriately setting or clearing the JAS bit (LIC1.3). If the part is configured for
hardware mode and the jitter attenuator is enabled, it will automatically be placed in the receive path. The
and
N
(where N = 0 to 3), 1.544MHz x 2
Figure
13-11. The jitter attenuator can be placed in either the receive path or the
80 of 122
N
(where N = 0 to 3), or 12.8MHz (available in CPU