DS1085Z-50 Maxim Integrated Products, DS1085Z-50 Datasheet - Page 13

• Manufacturer Part Number: DS1085Z-50
• Description: Timers & Support Products EconOscillator Frequ requency Synthesizer
• Manufacturer: Maxim Integrated Products

A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the
master to generate the STOP condition.
Figure 2. DATA TRANSFER ON 2-WIRE SERIAL BUS
Figures 2, 3, and 4 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state
of the R/W bit, two types of data transfer are possible:
1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus is not released.
The DS1085 can operate in the following two modes:
1) Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is
2) Slave transmitter mode: The first byte is received and handled as in the slave receiver mode.
master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte.
transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned.
received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is performed by hardware after reception
of the slave address and direction bit.
However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is
transmitted on SDA by the DS1085 while the serial clock is input on SCL. START and STOP
conditions are recognized as the beginning and end of a serial transfer.
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