MC100LVEL11DT

Manufacturer Part NumberMC100LVEL11DT
DescriptionClock Buffer 3.3V ECL 1:2 Diff
ManufacturerON Semiconductor
MC100LVEL11DT datasheets

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Specifications of MC100LVEL11DT

Number Of Outputs4Max Input Freq1000 MHz
Propagation Delay (max)0.405 nsSupply Voltage (max)+/- 3.8 V
Supply Voltage (min)+/- 3 VMaximum Operating Temperature+ 85 C
Minimum Operating Temperature- 40 CMounting StyleSMD/SMT
Package / CaseTSSOP-8Lead Free Status / RoHS StatusLead free / RoHS Compliant
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MC100LVEL11
3.3V ECL 1:2
Differential Fanout Buffer
Description
The MC100LVEL11 is a differential 1:2 fanout buffer. The device is
functionally similar to the E111 device but with higher performance
capabilities. Having within-device skews and output transition times
significantly improved over the E111, the LVEL11 is ideally suited for
those applications which require the ultimate in AC performance.
The differential inputs of the LVEL11 employ clamping circuitry to
maintain stability under open input conditions. If the inputs are left open
(pulled to V
) the Q outputs will go LOW.
EE
Features
•
330 ps Propagation Delay
•
5 ps Skew Between Outputs
•
High Bandwidth Output Transitions
•
The 100 Series Contains Temperature Compensation
•
PECL Mode Operating Range: V
CC
with V
= 0 V
EE
•
NECL Mode Operating Range: V
CC
with V
= −3.0 V to −3.8 V
EE
•
Internal Input Pulldown Resistors on D,
Pullup and Pulldown Resistors on D
•
Q Output will Default LOW with Inputs Open or at V
•
Pb−Free Packages are Available
Q
1
0
Q
2
0
Q
3
1
Q
4
1
Figure 1. Logic Diagram and Pinout Assignment
© Semiconductor Components Industries, LLC, 2009
January, 2009 − Rev. 11
= 3.0 V to 3.8 V
= 0 V
EE
8
V
CC
7
D
6
D
5
V
EE
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
1
http://onsemi.com
MARKING
DIAGRAMS*
8
8
1
KVL11
ALYW
G
SOIC−8
D SUFFIX
1
CASE 751
8
8
1
KV11
ALYWG
TSSOP−8
G
DT SUFFIX
1
CASE 948R
1
4
DFN8
MN SUFFIX
CASE 506AA
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Publication Order Number:
MC100LVEL11/D

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MC100LVEL11DT Summary of contents

  • Page 1

    MC100LVEL11 3.3V ECL 1:2 Differential Fanout Buffer Description The MC100LVEL11 is a differential 1:2 fanout buffer. The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times significantly improved over the ...

  • Page 2

    Table 1. PIN DESCRIPTION Pin Á Á Á Á Á Á Á Q0, Q0; Q1, Q1 Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ...

  • Page 3

    Table 4. LVPECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended Input ...

  • Page 4

    Table 6. AC CHARACTERISTICS V CC Symbol Characteristic f Maximum Toggle Frequency max t Propagation Delay to Output PLH t PHL t Within-Device Skew (Note 10) SKEW Device−to−Device (Note 11) Duty Cycle Skew (Note 12) t Random Clock Jitter (RMS) ...

  • Page 5

    ... ORDERING INFORMATION Device MC100LVEL11D MC100LVEL11DG MC100LVEL11DR2 MC100LVEL11DR2G MC100LVEL11DT MC100LVEL11DTG MC100LVEL11DTR2 MC100LVEL11DTR2G MC100LVEL11MNR4 MC100LVEL11MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D ...

  • Page 6

    ... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...

  • Page 7

    K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) D −T− G SEATING PLANE PACKAGE DIMENSIONS TSSOP−8 ...

  • Page 8

    ... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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