DS2152LN Maxim Integrated Products, DS2152LN Datasheet - Page 11

• Manufacturer Part Number: DS2152LN
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated Products

Specifications of DS2152LN

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 2.048 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current (max): 75 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.1 Transmit Side Digital Pins
PIN
46
47
53
33
51
34
35
37
52
48
49
50
43
42
41
38
TSYSCLK
TCHCLK
TCHBLK
TSSYNC
TDATA
TNEGO
TCLKO
TLCLK
TSYNC
TPOSO
TLINK
NAME
TPOSI
TESO
TCLK
TSER
TSIG
Transmit Channel Clock. A 192kHz clock that pulses high during the LSB of each
channel. Synchronous with TCLK when the transmit side elastic store is disabled.
Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for
parallel to serial conversion of channel data.
Transmit Channel Block. A user-programmable output that can be forced high or low
during any of the 24 T1 channels. Synchronous with TCLK when the transmit side
elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic
store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in
applications where not all T1 channels are used such as Fractional T1, 384kbps (H0),
768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-and-insert
applications, for external per-channel loopback, and for per-channel conditioning. See
Section
Transmit System Clock. 1.544MHz or 2.048MHz clock. Only used when the transmit
side elastic store function is enabled. Should be tied low in applications that do not use
the transmit side elastic store. Can be burst at rates up to 8.192MHz.
Transmit Link Clock. 4 kHz or 2kHz (ZBTSI) demand clock for the TLINK input. See
Section
Transmit Link Data. If enabled via TCR1.2, this pin will be sampled on the falling
edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs-bit position
(D4) or the Z-bit position (ZBTSI). See Section
Transmit Sync. A pulse at this pin will establish either frame or multiframe boundaries
for the transmit side. Via TCR2.2, the DS2152 can be programmed to output either a
frame or multiframe pulse at this pin. If this pin is set to output pulses at frame
boundaries, it can also be set via TCR2.4 to output double-wide pulses at signaling
frames. See Section
Transmit System Sync. Only used when the transmit side elastic store is enabled. A
pulse at this pin will establish either frame or multiframe boundaries for the transmit
side. Should be tied low in applications that do not use the transmit side elastic store.
Transmit Signaling Input. When enabled, this input will sample signaling bits for
insertion into outgoing PCM T1 data stream. Sampled on the falling edge of TCLK
when the transmit side elastic store is disabled. Sampled on the falling edge of
TSYSCLK when the transmit side elastic store is enabled.
Transmit Elastic Store Data Output. Updated on the rising edge of TCLK with data
out of the transmit side elastic store whether the elastic store is enabled or not. This pin
is normally tied to TDATA.
Transmit Data. Sampled on the falling edge of TCLK with data to be clocked through
the transmit side formatter. This pin is normally tied to TESO.
Transmit Positive Data Output. Updated on the rising edge of TCLKO with the
bipolar data out of the transmit side formatter. Can be programmed to source NRZ data
via the Output Data Format (CCR1.6) control bit. This pin is normally tied to TPOSI.
Transmit Negative Data Output. Updated on the rising edge of TCLKO with the
bipolar data out of the transmit side formatter. This pin is normally tied to TNEGI.
Transmit Clock Output. Buffered clock that is used to clock data through the transmit
side formatter (i.e., either TCLK or RCLKI). This pin is normally tied to TCLKI.
Transmit Positive Data Input. Sampled on the falling edge of TCLKI for data to be
Transmit Clock. A 1.544MHz primary clock. Used to clock data through the transmit
side formatter.
Transmit Serial Data. Transmit NRZ serial data. Sampled on the falling edge of
TCLK when the transmit side elastic store is disabled. Sampled on the falling edge of
TSYSCLK when the transmit side elastic store is enabled.
10
12
for details.
for details. Transmit Link Data [TLINK].
16
for details.
11 of 97
FUNCTION
12
for details.