MCP6561-E/MC Microchip Technology, MCP6561-E/MC Datasheet - Page 18

• Manufacturer Part Number: MCP6561-E/MC
• Description: Comparator ICs SNGL 18V Push/Pull Comparator E temp
• Manufacturer: Microchip Technology

Specifications of MCP6561-E/MC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCP6561/1R/2/4
4.6
In applications where low input bias current is critical,
PCB (Printed Circuit Board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 10
cause 5 pA of current to flow. This is greater than the
MCP6561/1R/2/4 family’s bias current at +25°C (1 pA,
typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure
FIGURE 4-9:
for Inverting Circuit.
1.
2.
DS22139A-page 18
Inverting Configuration (Figures 4-6 and 4-9):
a.
b.
Non-inverting Configuration
a.
b.
4-9.
PCB Surface Leakage
Connect the guard ring to the non-inverting
input pin (V
to the same reference voltage as the
comparator (e.g., V
Connect the inverting pin (V
pad without touching the guard ring.
Connect the non-inverting pin (V
input pad without touching the guard ring.
Connect the guard ring to the inverting input
pin (V
IN
-).
IN-
IN
Guard Ring
+). This biases the guard ring
Example Guard Ring Layout
12
DD
Ω. A 5V difference would
/2 or ground).
IN+
(Figure
IN
-) to the input
4-4):
IN
V
SS
+) to the
4.7
When designing the PCB layout it is critical to note that
analog and digital signal traces are adequately
separated to prevent signal coupling. If the comparator
output trace is at close proximity to the input traces
then large output voltage changes from, V
visa versa, may couple to the inputs and cause the
device output to oscillate. To prevent such oscillation,
the output traces must be routed away from the input
pins. The SC70-5 and SOT-23-5 are relatively immune
because the output pin OUT (pin 1) is separated by the
power pin V
long as the analog and digital traces remain separated
through out the PCB). However, the pinouts for the dual
and quad packages (SOIC, MSOP, TSSOP) have OUT
and -IN pins (pin 1 and 2) close to each other. The
recommended layout for these packages is shown in
Figure
FIGURE 4-10:
4.8
An unused amplifier in a quad package (MCP6564)
should be configured as shown in
circuit prevents the output from toggling and causing
crosstalk. It uses the minimum number of components
and draws minimal current (see
Figure
FIGURE 4-11:
OUTA
+INA
-INA
V
SS
4-10.
2-18).
PCB Layout Technique
Unused Comparators
DD
/V
SS
(pin 2) from the input pin +IN (as
¼ MCP6564
–
+
Recommended Layout.
Unused Comparators.
© 2009 Microchip Technology Inc.
V
DD
Figure
Figure 2-15
SS
OUTB
4-11. This
to V
V
+INB
-INB
DD
DD
and
or