DS1856E-050 Maxim Integrated Products, DS1856E-050 Datasheet - Page 16

• Manufacturer Part Number: DS1856E-050
• Description: Digital Potentiometer ICs
• Manufacturer: Maxim Integrated Products

Specifications of DS1856E-050

• Number Of Pots: Dual
• Taps Per Pot: 256
• Resistance: 50 KOhms
• Wiper Memory: Non Volatile
• Digital Interface: Serial (2-Wire)
• Operating Supply Voltage: 3.3 V, 5 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.85 V
• Package / Case: TSSOP-16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
*The final result must be XOR’ed with BB40h.
16
(hex)
Row
(hex)
Byte
A0
A8
B0
80
88
90
98
8C
A2
A4
A6
A8
AE
B0
B2
B4
B6
80
81
82
83
88
89
8E
8F
92
94
96
98
____________________________________________________________________
<9>
Temp Offset*
Mon1 Offset
Mon2 Offset
Mon3 Offset
Mon1 Scale
Mon2 Scale
Mon3 Scale
V
<0>
<8>
Chip Addr
V
Int Enable
<8>
<8>
PW1 msb
PW2 msb
<8>
<8>
Pwd Value
PW1 lsb
PW2 lsb
CC
CC
Tindex
Rshift
Rshift
Config
Name
Name
Mode
Config
Config
Offset
Offset
Res0
Res1
Row
Scale
Scale
Byte
Scale
Offset
1
0
0
1
0
1
0
1
bit
2
2
2
2
2
2
2
2
Int Enable
Reserved
Reserved
Reserved
Reserved
S
S
S
S
S
Byte 0/8
<8>
15
15
15
15
31
15
31
15
15
Temp
Bit7
Mode
2
2
2
2
7
7
7
7
MON3 Offset
Mon3 Scale
bit
2
2
2
2
2
2
2
2
Reserved
Reserved
PW1 msb
2
S
S
S
S
14
14
14
14
30
14
30
14
Word 0
14
8
bit
2
2
2
2
2
2
2
2
2
2
2
2
Reserved
Reserved
2
<4>
Byte 1/9
13
13
13
13
15
15
15
15
29
13
29
13
13
7
Config
Mon1
Mon3
Tindex
Bit6
Vcc
2
2
2
2
6
6
6
6
bit
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
12
12
12
12
14
14
14
14
28
12
28
12
12
6
TABLE 03 (CONFIGURATION)
bit
2
2
2
2
2
2
2
2
2
2
2
2
Reserved
Reserved
2
Byte 2/A
11
11
11
11
13
13
13
13
27
11
27
11
<4>
11
5
Mon1
Mon3
ADEN
Mon1
Bit5
Res0
EXPANDED BYTES
2
2
2
2
5
5
5
5
bit
Vcc Offset
Vcc Scale
Reserved
Reserved
2
2
2
2
2
2
2
2
2
2
2
2
1
1
PW1 lsb
2
Word 1
10
10
10
10
12
12
12
12
26
10
26
10
10
4
bit
Reserved
Reserved
2
2
2
2
2
2
Byte 3/B
2
2
2
2
2
2
2
<4>
11
11
11
11
25
25
ADFIX
Mon1
Mon3
9
9
9
9
3
9
9
Mon2
9
Bit4
Res1
2
2
2
2
4
4
4
4
bit
2
2
2
2
2
2
2
2
2
2
2
2
2
0
0
10
10
10
10
24
24
8
8
8
8
2
8
8
8
<8>
bit
chip addr
Reserved
Reserved
Reserved
Reserved
2
2
2
2
2
2
2
2
2
2
2
2
2
Byte 4/C
Reserved
23
23
7
7
7
7
9
9
9
9
1
7
7
7
Mon3
Bit3
2
2
2
2
3
3
3
3
MON1 Offset
Mon1 Scale
bit
2
2
Reserved
Reserved
PW2 msb
2
2
2
2
2
2
2
2
2
2
2
Memory Map (continued)
22
22
Word 2
6
6
6
6
8
8
8
8
0
6
6
6
<8>
bit
2
2
Reserved
Reserved
Reserved
Reserved
2
Reserved
2
2
2
2
2
2
2
2
2
2
Byte 5/D
21
21
-1
Reserved
5
5
5
5
7
7
7
7
5
5
Mon2
5
Bit2
2
2
2
2
2
2
2
2
bit
2
2
2
2
2
2
2
2
2
2
2
2
2
2
20
20
4
4
4
4
6
6
6
6
-2
4
4
4
<8>
bit
2
2
2
2
2
2
2
2
2
2
2
2
2
Reserved
Reserved
19
19
Byte 6/E
-3
3
3
3
3
5
5
5
5
3
3
Reserved
3
Mon2
Rshift
Internal Temp Offset*
Inv 1
TEN
Bit1
2
2
2
2
1
1
1
1
MON2 Offset
bit
Mon2 Scale
2
2
2
1
1
2
2
2
2
2
2
2
2
2
2
Reserved
18
18
PW2 lsb
-4
2
2
2
2
4
4
4
4
2
2
Word 3
2
bit
<8>
2
2
2
2
2
2
2
2
2
2
2
2
2
Reserved
Reserved
17
17
-5
Byte 7/F
1
1
1
1
3
3
3
3
1
1
Reserved
1
Rshift
Mon2
Inv 2
AEN
Bit0
2
2
2
2
0
0
0
0
bit
2
2
2
0
0
2
2
2
2
2
2
2
2
2
2
16
16
-6
0
0
0
0
2
2
2
2
0
0
0