IRLR8503 International Rectifier, IRLR8503 Datasheet - Page 3

• Manufacturer Part Number: IRLR8503
• Description: MOSFET N-CH 30V 44A DPAK
• Manufacturer: International Rectifier
• Series: HEXFET®r

Specifications of IRLR8503

• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 16 mOhm @ 15A, 10V
• Drain To Source Voltage (vdss): 30V
• Current - Continuous Drain (id) @ 25° C: 44A
• Vgs(th) (max) @ Id: 3V @ 250µA
• Gate Charge (qg) @ Vgs: 20nC @ 5V
• Input Capacitance (ciss) @ Vds: 1650pF @ 25V
• Power - Max: 62W
• Mounting Type: Surface Mount
• Package / Case: DPak, TO-252 (2 leads+tab), SC-63
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *IRLR8503

Power MOSFET Optimization for DC-DC Converters
While the IRLR8103V and IRLR8503 can and are be-
ing used in a variety of applications, they were designed
and optimized for low voltage DC-DC conversion in a
synchronous buck converter topology, specifically, mi-
croprocessor power applications. The IRLR8503 (Fig-
ure 1) was optimized for the control FET socket, while
the IRLR8103V was optimized for the synchronous
FET function.
Because of the inter-electrode capacitance (Figure 2)
of the Power MOSFET, specifying the R
vice is not enough to ensure good performance. An
optimization between R
formed to insure the best performing MOSFET for a
given application. Both die size and device architec-
ture must be varied to achieve the minimum possible
in-circuit losses. This is independently true for both
control FET and synchronous FET. Unfortunately, the
capacitances of a FET are non-linear and voltage de-
pendent. Therefore, it is inconvenient to specify and
use them effectively in switching power supply power
loss estimations. This was well understood years ago
and resulted in changing the emphasis from capaci-
tance to gate charge on Power MOSFET data sheets.
International Rectifier has recently taken the industry
a step further by specifying new charge parameters
that are even more specific to DC-DC converter de-
sign (Table 2). In order to understand these parameters,
it is best to start with the in-circuit waveforms in Fig-
ure 3 & Figure 4.
www.irf.com
Device Capacitance
Figure 1 – Application
C
GS
Table 1 – Traditional Charge Parameters
C
C
Topology
+ C
GS
GD
GD
IRLR8503
(Cont FET)
IRLR8103V
(Sync FET)
Corresponding Charge Parameter
DSON
CGD
CGS
and charge must be per-
Figure 2 – Inter-electrode
Capacitance
Q
Q
Q
GS
GD
G
DSON
of the de-
CDS
VGTH
The waveforms are broken into segments correspond-
ing to charge parameters. These, in turn, correspond
to discrete time segments of the switching waveform.
g1
g2
Losses may be broken into four categories: conduc-
tion loss, gate drive loss, switching loss, and output
loss. The following simplified power loss equation is
true for both MOSFETs in a synchronous buck con-
verter:
For the synchronous FET, the P
virtually zero and is ignored.
New Charge
P
Parameter
(Control FET)
Figure 3 – Control FET
Q
LOSS
Q
Q
QSwitch
Q
Q
Q
SWITCH
GCONT
GSYNC
OSS
GS1
GS2
QG
Equivalent Circuit
QGD
Figure 5 – Q
Drain Voltage
= P
Waveform
VIN
N2
Sync FET
N1
Cont FET
CONDUCTION
Table 2 – New Charge Parameters
Charge supplied to C
Drain Current
Gate Voltage
Charge during control FET switching
Synchronous FET Total Q
period of control FET switching
Post-Threshold Gate Charge
Pre-Threshold Gate Charge
OSS
Combines Q
SN
Control FET Total Q
+ P
Coss1
2 n
Coss2
2n
Output charge
Description
GATE DRIVE
GS2
OSS
0 V
VGTH
IRLR8503
and Q
during the Q
Gate Voltage
Figure 4 – Sync FET
G
SWITCH
+ P
Body
Diode
Current
Dead
Time
(V
G
Figure 6 – Q
GD
0 A
DS
Waveforms
QG (Sync FET)
SWITCH
Waveform
≤ 0)
Drain Current
Drain Voltage
term becomes
Switch node voltage
GD
N1 Gate
Voltage
N1 Current
N1 Coss Discharge
N2 Coss Charge
+ P
(VSN)
Waveform
Figure 3
Figure 5
Figure 6
Figure 4
OSS
OUTPUT
+
3