SI3201-FSR Silicon Laboratories Inc, SI3201-FSR Datasheet - Page 81

• Manufacturer Part Number: SI3201-FSR
• Description: SLIC 1-CH 60dB 41mA 3.3V/5V 16-Pin SOIC EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3201-FSR

• Package: 16SOIC EP
• Number Of Channels Per Chip: 1
• Longitudinal Balanced: 60 dB
• Loop Current: 41 mA
• Minimum Operating Supply Voltage: 3.13 V
• Typical Operating Supply Voltage: 3.3|5 V
• Typical Supply Current: 88 mA

Register 52. FSK Data
Reset settings = 0000_0000
Register 63. Loop Closure Debounce Interval
Reset settings = 0101_0100
Name
Name
Type
Type
Bit
7:1
Bit
7:0
0
Bit
Bit
Reserved
LCD[7:0]
FSKDAT
Name
Name
D7
D7
D6
D6
Read returns zero.
FSK Data.
When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6), this
bit serves as the buffered input for FSK generation bit stream data.
Loop Closure Debounce Interval for Automatic Ringing.
This register sets the loop closure debounce interval for the ringing silent period when
using automatic ringing cadences. The value may be set between 0 ms (0x00) and
159 ms (0x7F) in 1.25 ms steps.
D5
D5
D4
D4
LCD[7:0]
Rev. 1.0
D3
D3
Function
Function
D2
D2
D1
D1
FSKDAT
R/W
D0
D0
Si3216
81