AD9764AR Analog Devices Inc, AD9764AR Datasheet
AD9764AR
Specifications of AD9764AR
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AD9764AR Summary of contents
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FEATURES Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 14-Bit Resolution Excellent SFDR and IMD Differential Current Outputs Power Dissipation: 190 Power-Down ...
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AD9764–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL + MIN MAX Differential Nonlinearity (DNL + MIN MAX ANALOG ...
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DYNAMIC SPECIFICATIONS Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (f CLOCK Output Settling Time (t ) (to 0.1%) ST Output Propagation Delay ( Glitch Impulse 1 Output Rise Time (10% to 90%) 1 Output Fall Time (10% to ...
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... S t LPW IOUTA OR IOUTB 0.1% Figure 1. Timing Diagram Max Units Model +6.5 V AD9764AR +6.5 V AD9764ARU – +85 C +0.3 V AD9764-EB +6 Small Outline IC TSSOP. DVDD + 0.3 V DVDD + 0.3 V THERMAL CHARACTERISTICS AVDD + 0.3 V Thermal Resistance AVDD + 0.3 V 28-Lead 300 mil SOIC AVDD + 0 71.4 C/W +0 ...
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Pin No. Name Description 1 DB13 Most Significant Data Bit (MSB). 2–13 DB12–DB1 Data Bits 1–12. 14 DB0 Least Significant Data Bit (LSB). 15 SLEEP Power-Down Control Input. Active High. Contains active pull-down circuit; it may be left unterminated if ...
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AD9764 DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. ...
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Typical AC Characterization Curves (AVDD = +5 V, DVDD = + mA, 50 OUTFS MSPS 80 25 MSPS 75 50 MSPS 70 65 100 MSPS 0 ...
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AD9764 –70 –75 2ND HARMONIC –80 3RD HARMONIC –85 4TH HARMONIC –90 –95 000.0E+0 40.0E+6 80.0E+6 120.0E+6 Figure 12. THD vs CLOCK MHz OUT 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0 4000 ...
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V REFIO I REF 0 SET 2k +5V CLOCK FUNCTIONAL DESCRIPTION Figure 21 shows a simplified block diagram of the AD9764. The AD9764 consists of a large PMOS current source array that is capable of providing up to ...
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AD9764 REFERENCE OPERATION The AD9764 contains an internal 1.20 V bandgap reference that can be easily disabled and overridden by an external reference. REFIO serves as either an input or output, depending on whether the internal or external reference is ...
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AVDD 1.2V AD1580 The second method may be used in a dual-supply system in which the common-mode voltage of REFIO is fixed, and I varied by an external voltage applied fier. An example of this ...
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AD9764 1.25 V for 1.00 V for an I OUTFS Operation beyond the positive compliance range will induce clipping of the output signal which severely degrades the AD9764’s linearity and distortion performance. For applications ...
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Since the AD9764 is capable of being updated up to 125 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. Operating the AD9764 with reduced logic swings and a corresponding digital supply ...
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AD9764 APPLYING THE AD9764 OUTPUT CONFIGURATIONS The following sections illustrate some typical output configura- tions for the AD9764. Unless otherwise noted assumed that I is set to a nominal 20 mA. For applications requir- OUTFS ing the optimum ...
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I and R can be selected as long as the positive compli- OUTFS LOAD ance range is adhered to. One additional consideration in this mode is the integral nonlinearity (INL) as discussed in the Ana- log Output section of this ...
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AD9764 MULTITONE PERFORMANCE CONSIDERATIONS AND CHARACTERIZATION The frequency domain performance of high speed DACs has traditionally been characterized by analyzing the spectral output of a reconstructed full-scale (i.e., 0 dBFS), single-tone sine wave at a particular output frequency and update ...
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DAC can be evaluated. Nonlinearities associated with the DAC will create spurious tones of which some may fall back into the “empty” channel thus limiting a channel’s carrier-to-noise ratio. Other spurious components falling outside the band of interest ...
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AD9764 Figure 41. Evaluation Board Schematic –18– REV. B ...
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REV. B Figure 42. Silkscreen Layer—Top Figure 43. Component Side PCB Layout (Layer 1) –19– AD9764 ...
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AD9764 Figure 44. Ground Plane PCB Layout (Layer 2) Figure 45. Power Plane PCB Layout (Layer 3) –20– REV. B ...
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REV. B Figure 46. Solder Side PCB Layout (Layer 4) Figure 47. Silkscreen Layer—Bottom –21– AD9764 ...
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AD9764 PIN 1 0.0118 (0.30) 0.0040 (0.10) PIN 1 0.006 (0.15) 0.002 (0.05) SEATING OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 1 ...