74FCT163244APAG Integrated Device Technology (Idt), 74FCT163244APAG Datasheet - Page 5

• Manufacturer Part Number: 74FCT163244APAG
• Description: Buffer/Line Driver 16-CH Non-Inverting 3-ST CMOS 48-Pin TSSOP Tube
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 74FCT163244APAG

• Package: 48TSSOP
• Logic Family: FCT
• Logic Function: Buffer/Line Driver
• Number Of Outputs Per Chip: 16
• Output Type: 3-State
• Input Signal Type: Single-Ended
• Maximum Propagation Delay Time @ Maximum Cl: 4.8@3.3V ns
• Typical Quiescent Current: 0.1 uA
• Polarity: Non-Inverting

TEST CIRCUITS AND WAVEFORMS
IDT74FCT163244A/C
3.3V CMOS 16-BIT BUFFER/LINE DRIVER
ASYNCHRONOUS CONTROL
Generator
SYNCHRONOUS CONTROL
Pulse
CLOCK ENABLE
INPUT TRANSITION
INPUT TRANSITION
OPPOSITE PHASE
PRESET
SAME PHASE
PRESET
TIMING
CLEAR
CLEAR
V
INPUT
OUTPUT
INPUT
DATA
IN
ETC.
ETC.
Set-up, Hold, and Release Times
Test Circuits for All Outputs
R
T
Propagation Delay
D.U.T
.
V
CC
t
PLH
t
PLH
t
t
SU
SU
V
OUT
t
REM
t
C
H
50pF
t
t
L
PHL
PHL
t
H
500
Ω
500
Ω
V
V
1.5V
1.5V
1.5V
3V
0V
3V
0V
Open
GND
OH
OL
3V
1.5V
3V
1.5V
3V
1.5V
0V
0V
3V
1.5V
0V
0V
6v
5
DEFINITIONS:
C
R
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
3. if V
SWITCH POSITION
L
T
= Load capacitance: includes jig and probe capacitance.
= Termination resistance: should be equal to Z
NORMALLY
NORMALLY
CONTROL
HIGH-LOW-HIGH
CC
LOW-HIGH-LOW
OUTPUT
OUTPUT
is below 3V, input voltage swings should be adjusted not to exceed V
INPUT
All Other Tests
HIGH
Disable High
Disable Low
Enable High
LOW
Enable Low
Open Drain
Test
PULSE
PULSE
SWITCH
SWITCH
GND
ENABLE
Enable and Disable Times
6V
t
t
PZH
PZL
Pulse Width
INDUSTRIAL TEMPERATURE RANGE
1.5V
1.5V
3V
0V
t
PHZ
OUT
t
F
W
≤ 2.5ns; t
of the Pulse Generator.
DISABLE
t
PLZ
Switch
GND
Open
6V
R
≤ 2.5ns.
0.3V
0.3V
V
3V
1.5V
0V
3V
V
0V
OL
OH
1.5V
1.5V
CC
.