82V3280EQG Integrated Device Technology (Idt), 82V3280EQG Datasheet - Page 17

• Manufacturer Part Number: 82V3280EQG
• Description: WAN PLL 100-Pin TQFP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 82V3280EQG

• Package: 100TQFP
• Operating Temperature: -40 to 85 °C

Table 1: Pin Description (Continued)
Pin Description
IDT82V3280
VDD_DIFF1
VDD_DIFF2
VDD_AMI
VDDD1
VDDD2
VDDD3
VDDD4
VDDD5
VDDD6
VDDD7
VDDA1
VDDA2
VDDA3
Name
TRST
RDY
TMS
TCK
TDO
TDI
Pin No.
75
23
21
12
16
13
50
61
85
86
19
91
26
33
39
2
7
9
6
pull-down
pull-down
pull-up
pull-up
Power
Power
Power
Power
Power
I/O
O
O
I
I
I
I
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Type
-
-
-
-
-
JTAG (per IEEE 1149.1)
RDY: Ready/Data Acknowledge
In Multiplexed and Intel modes, a high level on this pin indicates that a read/write cycle is
completed. A low level on this pin indicates that wait state must be inserted.
In Motorola mode, a low level on this pin indicates that valid information on the data bus is
ready for a read operation or acknowledges the acceptance of the written data during a write
operation.
In EPROM and Serial modes, this pin should be connected to ground.
TRST: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK.
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely
retain their state.
TDI: JTAG Test Data Input
The test data is input on this pin. It is clocked into the device on the rising edge of TCK.
TDO: JTAG Test Data Output
The test data is output on this pin. It is clocked out of the device on the falling edge of TCK.
TDO pin outputs a high impedance signal except during the process of data scanning.
This pin can indicate the interrupt of T0 selected input clock fail, as determined by the
LOS_FLAG_ON_TDO bit (b6, 0BH). Refer to
VDDDn: 3.3 V Digital Power Supply
Each VDDDn should be paralleled with ground through a 0.1 µF capacitor.
VDDAn: 3.3 V Analog Power Supply
Each VDDAn should be paralleled with ground through a 0.1 µF capacitor.
VDD_AMI: 3.3 V Power Supply for AMI I/O
VDD_DIFF1: 3.3 V Power Supply for OUT6
VDD_DIFF2: 3.3 V Power Supply for OUT7
Power & Ground
17
Description
Chapter 3.8.1 Input Clock Validity
1
December 9, 2008
for details.
WAN PLL