72403L10P Integrated Device Technology (Idt), 72403L10P Datasheet

72403L10P

Manufacturer Part Number

72403L10P

Description

FIFO Mem Async Dual Depth/Width Uni-Dir 64 x 4 16-Pin PDIP

Manufacturer

Integrated Device Technology (Idt)

Datasheet

1.72403L10P.pdf (9 pages)

Specifications of 72403L10P

Package

16PDIP

Configuration

Dual

Bus Directional

Uni-Directional

Density

256 Bit

Organization

64x4

Data Bus Width

4 Bit

Timing Type

Asynchronous

Expansion Type

Depth|Width

Typical Operating Supply Voltage

5 V

Operating Temperature

0 to 70 Â°C

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FEATURES:

• • • • •

DESCRIPTION:

First-ln/First-Out memories organized 64 words by 4 bits. The IDT72403 also

FUNCTIONAL BLOCK DIAGRAM

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.

FAST is a trademark of National Semiconductor, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

0-3

First-ln/First-Out Dual-Port memory

64 x 4 organization (IDT72401/72403)

RAM-based FIFO with low falI-through time

Low-power consumption

— Active: 175mW (typ.)

Maximum shift rate — 45MHz

High data output drive capability

Asynchronous and simultaneous read and write

Fully expandable by bit width

Fully expandable by word depth

IDT72403 have Output Enable pin to enable output data

High-speed data communications applications

High-performance CMOS technology

Available in CERDIP, plastic DIP and SOIC

Military product compliant to MlL-STD-883, Class B

Standard Military Drawing #5962-86846 and

5962-89523 is listed on this function.

Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available

(plastic packages only)

The IDT72401 and IDT72403 are asynchronous high-performance

Integrated Device Technology, Inc.

CONTROL

MASTER

DATA

RESET

LOGIC

INPUT

CMOS PARALLEL FIFO

64 x 4 and 64 x 5

WRITE MULTIPLEXER

READ MULTIPLEXER

WRITE POINTER

READ POINTER

MEMORY

ARRAY

has an Output Enable (OE) pin. The FlFOs accept 4-bit data at the data input

to the output while all other data shifts down one location in the stack. The Input

Ready (IR) signal acts like a flag to indicate when the input is ready for new

data (IR = HIGH) or to signal when the FIFO is full (IR = LOW). The IR signal

can also be used to cascade multiple devices together. The Output Ready (OR)

signal is a flag to indicate that the output remains valid data (OR = HIGH) or

to indicate that the FIFO is empty (OR = LOW). The OR can also be used to

cascade multiple devices together.

to form composite signals.

the data outputs of the previous device. The IR pin of the receiving device is

connected to the SO pin of the sending device and the OR pin of the sending

device is connected to the Shift In (SI) pin of the receiving device.

FIFO to be used as a buffer between two digital machines of widely varying

operating frequencies. The 45MHz speed makes these FlFOs ideal for high-

speed communication and controller applications.

of MIL-STD-883, Class B.

A Shift Out (SO) signal causes the data at the next to last word to be shifted

Width expansion is accomplished by logically ANDing the IR and OR signals

Depth expansion is accomplished by tying the data inputs of one device to

Reading and writing operations are completely asynchronous allowing the

Military grade product is manufactured in compliance with the latest revision

-D

). The stored data stack up on a first-in/first-out basis.

MASTER

OUTPUT

ENABLE

DATA

RESET

OCTOBER 2005

(IDT72403 only)

0-3

2747 drw01

IDT72401

IDT72403

DSC-2747/10

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72403L10P Summary of contents

Page 1

FEATURES: • • • • • First-ln/First-Out Dual-Port memory • • • • • organization (IDT72401/72403) • • • • • RAM-based FIFO with low falI-through time • • • • • Low-power consumption — Active: 175mW ...

Page 2

IDT72401/72403 CMOS PARALLEL FIFO PIN CONFIGURATIONS IDT72401/IDT72403 (1) NC/ GND ...

Page 3

IDT72401/72403 CMOS PARALLEL FIFO OPERATING CONDITIONS (Commercial 5.0V ± 10 0°C to +70°C; Military Symbol Parameter t (1) Shift in HIGH Time SIH t Shift in LOW ...

IDT72401/72403 CMOS PARALLEL FIFO TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load CAPACITANCE (T = +25° 1.0MHz) A Symbol Parameter Conditions C ...

Page 5

IDT72401/72403 CMOS PARALLEL FIFO FUNCTIONAL DESCRIPTION The FIFO is designed using a dual port RAM architecture as opposed to the traditional shift register approach. This FIFO architecture has a write pointer, ...

Page 6

IDT72401/72403 CMOS PARALLEL FIFO ( (1) INPUT DATA NOTES: 1. FIFO is initially full pulse is applied held HIGH soon as IR becomes HIGH ...

Page 7

IDT72401/72403 CMOS PARALLEL FIFO (1) OR DATA OUTPUT NOTE: 1. FIFO initially empty. t MRW MR IR (1) ( DATA OUTPUT NOTE: 1. Worst case, FIFO initially full. OE DATA ...

Page 8

IDT72401/72403 CMOS PARALLEL FIFO COMPOSITE D 0 INPUT D READY SHIFT ...

Page 9

ORDERING INFORMATION IDT XXXXX X X Device Type Power Speed Package NOTE: 1. Industrial temperature range is available by special order. DATASHEET DOCUMENT HISTORY 07/10/2003 pgs and 9. 10/27/2005 pgs CORPORATE HEADQUARTERS 6024 Silver Creek Valley ...

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