72V293L10PFI Integrated Device Technology (Idt), 72V293L10PFI Datasheet - Page 15

• Manufacturer Part Number: 72V293L10PFI
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18/128K x 9 80-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V293L10PFI

• Package: 80TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 1.125 Mb
• Organization: 64Kx18|128Kx9
• Data Bus Width: 18|9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: -40 to 85 °C

NOTES:
1. When programming the IDT72V293 with an input bus width of x9 and output bus width of x18, 4 write cycles will be required. When Reading the IDT72V293 with an output bus
2. A total of 6 program/ read cycles will be required for x9 bus width if both the input and output bus widths are set to x9.
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
IDT72V223/72V233/72V243/72V253/72V263/
72V273/72V283/72V293
D/Q17
D/Q17
IDT72V223/72V233/72V243/72V253/72V263/72V273/
72V283/72V293
width of x9 and input bus width of x18, 4 read cycles will be required.
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
1st Parallel Offset Write/Read Cycle
D/Q8
D/Q8
D/Q8
D/Q8
D/Q16
D/Q16
16
16
15
16
16
15
15
14
14
16
16
15
8
8
14
14
13
13
EMPTY OFFSET REGISTER
13
13
12
15
1
5
12
EMPTY OFFSET REGISTER
EMPTY OFFSET REGISTER
7
7
FULL OFFSET REGISTER
Data Inputs/Outputs
Data Inputs/Outputs
FULL OFFSET REGISTER
FULL OFFSET REGISTER
12
11
12
11
⎯
10
10
14
11
11
14
6
6
x18 Bus Width
10
10
9
9
D/Q8
D/Q8
13
13
5
5
9
9
8
8
8
(2)
8
⎯
12
12
4
4
7
7
7
7
x9 Bus Width
6
6
6
6
# of Bits Used
Figure 3. Programmable Flag Offset Programming Sequence
11
11
3
5
5
3
5
5
4
4
4
4
10
10
3
3
3
2
2
3
2
2
2
2
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
1
1
1
1
9
1
9
1
Non-Interspersed
Parity
Interspersed
Parity
TM
15
NARROW BUS FIFO
TM
NARROW BUS FIFO
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
5th Parallel Offset Write/Read Cycle
6th Parallel Offset Write/Read Cycle
1st Parallel Offset Write/Read Cycle
D/Q8
D/Q8
D/Q8
D/Q8
D/Q8
D/Q8
IDT72V293
# of Bits Used:
10 bits for the IDT72V223
11 bits for the IDT72V233
12 bits for the IDT72V243
13 bits for the IDT72V253
14 bits for the IDT72V263
15 bits for the IDT72V273
16 bits for the IDT72V283
17 bits for the IDT72V293
Note: All unused bits of the
LSB & MSB are don't care
16
x9 to x9 Mode
16
8
8
15
15
EMPTY OFFSET REGISTER
EMPTY OFFSET REGISTER
EMPTY OFFSET REGISTER
7
7
FULL OFFSET REGISTER
FULL OFFSET REGISTER
FULL OFFSET REGISTER
(2)
⎯
x9 Bus Width
14
14
6
6
13
13
5
5
COMMERCIAL AND INDUSTRIAL
# of Bits Used:
10 bits for the IDT72V233
11 bits for the IDT72V243
12 bits for the IDT72V253
13 bits for the IDT72V263
14 bits for the IDT72V273
15 bits for the IDT72V283
16 bits for the IDT72V293
Note: All unused bits of the
LSB & MSB are don't care
9 bits for the IDT72V223
12
12
4
4
All Other Modes
TEMPERATURE RANGES
11
19
11
FEBRUARY 11, 2009
3
3
10
18
10
2
2
4666 drw06
17
17
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
1
9
1
9