72T1875L5BBI Integrated Device Technology (Idt), 72T1875L5BBI Datasheet - Page 45

• Manufacturer Part Number: 72T1875L5BBI
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 16K x 18/32K x 9 144-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T1875L5BBI

• Package: 144BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 288 Kb
• Organization: 16Kx18|32Kx9
• Data Bus Width: 9/18 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: -40 to 85 °C

NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
6. RCS is LOW.
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
7. RCS = LOW.
WCLK
RCLK
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
WCLK
RCLK
WEN
REN
PAF
WEN
rising edge of WCLK and the rising edge of RCLK is less than t
In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 2,048 for the IDT72T1845, 4,096 for the IDT72T1855, 8,192 for the IDT72T1865, 16,384 for the IDT72T1875,
32,768 for the IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the IDT72T18105, 262,144 for the IDT72T18115 and 524,288 for the IDT72T18125. If both x9 Input and x9
Output bus Widths are selected, D = 4,096 for the IDT72T1845, 8,192 for the IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the IDT72T1875, 65,536 for the IDT72T1885,
131,072 for the IDT72T1895, 262,144 for the IDT72T18105, 524,288 for the IDT72T18115 and 1,048,576 for the IDT72T18125.
In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 2,049 for the IDT72T1845, 4,097 for the IDT72T1855, 8,193 for the IDT72T1865, 16,385 for the IDT72T1875,
32,769 for the IDT72T1885, 65,537 for the IDT72T1895, 131,073 for the IDT72T18105, 262,145 for the IDT72T18115 and 524,289 for the IDT72T18125. If both x9 Input and x9
Output bus Widths are selected, D = 4,097 for the IDT72T1845, 8,193 for the IDT72T1855, 16,385 for the IDT72T1865, 32,769 for the IDT72T1875, 65,537 for the IDT72T1885,
131,073 for the IDT72T1895, 262,145 for the IDT72T18105, 524,289 for the IDT72T18115 and 1,048,577 for the IDT72T18125.
rising edge of RCLK and the rising edge of WCLK is less than t
REN
SKEW2
SKEW2
PAE
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
t
CLKH
t
CLKL
Figure 24. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
ENS
t
t
CLKL
n words in FIFO
n + 1 words in FIFO
ENS
t
CLKL
D - (m +1) words in FIFO
t
ENH
(2)
t
SKEW2
,
1
(3)
t
ENH
(4)
t
PAES
(2)
1
2
SKEW2
SKEW2
, then the PAF deassertion time may be delayed one extra WCLK cycle.
, then the PAE deassertion may be delayed one extra RCLK cycle.
2
45
t
PAFS
t
ENS
t
ENS
n + 1 words in FIFO
n + 2 words in FIFO
2Kx18/4Kx9, 4Kx18/
t
ENH
t
SKEW2
t
ENH
(2)
(3)
D - m words in FIFO
(3)
,
1
1
COMMERCIAL AND INDUSTRIAL
(2)
t
PAES
TEMPERATURE RANGES
PAES
2
PAFS
FEBRUARY 10, 2009
2
t
PAFS
). If the time between the
). If the time between the
n words in FIFO
n + 1 words in FIFO
D-(m+1) words
in FIFO
5909 drw28
5909 drw27
(2)
(2)
,
(3)