XC2S100E-6FT256I Xilinx Inc, XC2S100E-6FT256I Datasheet - Page 106

• Manufacturer Part Number: XC2S100E-6FT256I
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 256-Pin FTBGA
• Manufacturer: Xilinx Inc

Specifications of XC2S100E-6FT256I

• Package: 256FTBGA
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 182
• Ram Bits: 40960

Spartan-IIE FPGA Family: Pinout Tables
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
FG676 Differential Clock Pins
Additional FG676 Package Pins
106
I/O, L2N_YY
I/O, L1P_YY
I/O, L1N_YY
I/O, L0P
I/O, L0N
I/O
TCK
VCCINT Pins
VCCO Bank 0 Pins
VCCO Bank 1 Pins
VCCO Bank 2 Pins
VCCO Bank 3 Pins
VCCO Bank 4 Pins
VCCO Bank 5 Pins
VCCO Bank 6 Pins
VCCO Bank 7 Pins
Clock
GCK0
GCK1
GCK2
GCK3
K17
U16
C19
E24
P17
U14
U12
P10
Function
H8
C5
H3
Pad Name
Bank
4
5
1
0
H19
U17
C22
H24
R17
U15
U13
R10
L10
C8
K9
Bank
0
0
0
0
0
0
-
Pin
C4
E5
B4
A3
B3
A4
A2
AF14
AF13
A14
A13
Pin
D11
D16
L17
K18
T18
V16
V10
Output Option
V9
T4
J9
L4
LVDS Async.
XC2S600E
XC2S600E
P Input
All
All
All
-
-
www.xilinx.com
GCK0, I
GCK1, I
GCK2, I
GCK3, I
Name
T10
V18
T23
V17
V11
J18
J10
J16
L18
T9
L9
Option
VREF
-
-
-
-
-
-
-
AC16
AC11
M10
U18
K10
T17
L23
J11
J17
W8
U9
I/O, L2N_YY
I/O, L1P_YY
I/O, L1N_YY
XC2S400E
AE14
AE13
B14
B13
Pin
TCK
I/O
I/O
Device-Specific Pinouts
-
N Input
AD19
W19
W24
M17
AD5
K11
U10
K12
K14
N10
W3
DS077-4 (2.3) June 18, 2008
I/O (DLL), L126N
I/O (DLL), L126P
I/O (DLL), L23P
I/O (DLL), L23N
Product Specification
I/O, L2N_YY
I/O, L1P_YY
I/O, L1N_YY
XC2S600E
I/O, L0N_Y
I/O, L0P_Y
Name
TCK
I/O
AB24
AD22
AD8
U11
N17
AB3
K16
K13
K15
E3
-
R