XC2S100E-6TQ144I Xilinx Inc, XC2S100E-6TQ144I Datasheet - Page 18

• Manufacturer Part Number: XC2S100E-6TQ144I
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 144-Pin TQFP
• Manufacturer: Xilinx Inc

Specifications of XC2S100E-6TQ144I

• Package: 144TQFP
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 102
• Ram Bits: 40960

Spartan-IIE FPGA Family: Functional Description
edges arrive at internal flip-flops in synchronism with clock
edges arriving at the input.
In addition to eliminating clock-distribution delay, the DLL
provides advanced control of multiple clock domains. The
DLL provides four quadrature phases of the source clock,
can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4,
5, 8, or 16. The phase-shifted output have optional
duty-cycle correction
The DLL also operates as a clock mirror. By driving the out-
put from a DLL off-chip and then back on again, the DLL can
be used to deskew a board level clock among multiple Spar-
tan-IIE devices.
In order to guarantee that the system clock is operating cor-
rectly prior to the FPGA starting up after configuration, the
18
CLKIN
Figure 12: Delay-Locked Loop Block Diagram
CLKDV_DIVIDE=2
DUTY_CYCLE_CORRECTION=FALSE
DUTY_CYCLE_CORRECTION=TRUE
CLK180
CLK270
CLK180
CLK270
CLKDV
CLK2X
CLK90
CLK90
CLKIN
CLK0
CLK0
Figure 13: DLL Output Characteristics
Control
0
Delay Line
Variable
90 180 270
(Figure
t
CLKFB
13).
CLKOUT
0
90 180 270
ds077-2_10_070203
Clock
Distribution
Network
x132_07_092599
www.xilinx.com
DLL can delay the completion of the configuration process
until after it has achieved lock. If the DLL uses external feed-
back, apply a reset after startup to ensure consistent lock-
ing to the external signal. See Xilinx Application Note
XAPP174
Boundary Scan
Spartan-IIE devices support all the mandatory bound-
ary-scan instructions specified in the IEEE standard 1149.1.
A Test Access Port (TAP) and registers are provided that
implement the EXTEST, INTEST, SAMPLE/PRELOAD,
BYPASS, IDCODE, and HIGHZ instructions. The TAP also
supports two USERCODE instructions, internal scan
chains, and configuration/readback of the device.
The TAP uses dedicated package pins that always operate
using LVTTL. For TDO to operate using LVTTL, the V
Bank 2 must be 3.3V. Otherwise, TDO switches rail-to-rail
between ground and V
(TDI, TMS, TCK) do not have a V
ate with either 2.5V or 3.3V input signaling levels. TDI, TMS,
and TCK hava a default internal weak pull-up resistor, and
TDO has no default resistor. Bitstream options allow setting
any of the four TAP pins to have an internal pull-up,
pull-down, or neither.
Boundary-scan operation is independent of individual IOB
configurations, and unaffected by package type. All IOBs,
including unbonded ones, are treated as independent
3-state bidirectional pins in a single scan chain. Retention of
the bidirectional test capability after configuration facilitates
the testing of external interconnections.
Table 8
Spartan-IIE FPGAs. Internal signals can be captured during
EXTEST by connecting them to unbonded or unused IOBs.
They may also be connected to the unused outputs of IOBs
defined as unidirectional input pins.
Table 8: Boundary-Scan Instructions
Boundary-Scan
Command
PRELOAD
CFG_OUT
SAMPLE/
EXTEST
CFG_IN
USER1
USER2
lists the boundary-scan instructions supported in
for more information on DLLs.
Code[4:0]
Binary
00000
00001
00010
00011
00100
00101
CCO
. The boundary-scan input pins
DS077-2 (v2.3) June 18, 2008
CCO
Enables boundary-scan
Enables boundary-scan
SAMPLE/PRELOAD
Access user-defined
Access user-defined
configuration bus for
configuration bus for
EXTEST operation
requirement and oper-
Product Specification
Configuration
Description
Access the
Access the
Readback
operation
register 1
register 2
CCO
for
R