XC2S150E-6PQG208C Xilinx Inc, XC2S150E-6PQG208C Datasheet - Page 27

• Manufacturer Part Number: XC2S150E-6PQG208C
• Description: FPGA Spartan®-IIE Family 150K Gates 3888 Cells 357MHz 0.15um Technology 1.8V 208-Pin PQFP
• Manufacturer: Xilinx Inc

Specifications of XC2S150E-6PQG208C

• Package: 208PQFP
• Family Name: Spartan®-IIE
• Device Logic Cells: 3888
• Device Logic Units: 864
• Device System Gates: 150000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 146
• Ram Bits: 49152

Multiple Spartan-IIE FPGAs can be configured using the
Slave Parallel mode, and be made to start-up simulta-
neously. To configure multiple devices in this way, wire the
individual CCLK, Data, WRITE, and BUSY pins of all the
devices in parallel. The individual devices are loaded sepa-
rately by asserting the CS pin of each device in turn and
writing the appropriate data. Sync-to-DONE start-up timing
is used to ensure that the start-up sequence does not begin
until all the FPGAs have been loaded. See
page
Write
When using the Slave Parallel Mode, write operations send
packets of byte-wide configuration data into the FPGA.
Figure 21, page 28
used to load data into the Spartan-IIE FPGA. This is an
expansion of the "Load Configuration Data Frames" block in
Figure 16, page
DS077-2 (v2.3) June 18, 2008
Product Specification
23.
DONE
INIT
PROGRAM
DATA[7:0]
CCLK
WRITE
BUSY
R
23.
shows a flowchart of the write sequence
CS(0)
Figure 20: Slave Parallel Configuration Circuit Diagram
M0
D0:D7
CCLK
WRITE
BUSY
CS
PROGRAM
DONE
M1 M2
Spartan-IIE
Start-up,
GND
www.xilinx.com
INIT
The timing for Slave Parallel mode is shown in
page
For the present example, the user holds WRITE and CS
Low throughout the sequence of write operations. Note that
when CS is asserted on successive CCLKs, WRITE must
remain either asserted or deasserted. Otherwise an abort
will be initiated, as in the next section.
1. Drive data onto D0-D7. Note that to avoid contention,
2. On the rising edge of CCLK: If BUSY is Low, the data is
3. Repeat steps 1 and 2 until all the data has been sent.
4. Deassert CS and WRITE.
CS(1)
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more than one device’s CS should be asserted.
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance will instead
occur on the first clock after BUSY goes Low, and the
data must be held until this happens.
50.
Spartan-IIE FPGA Family: Functional Description
M0
D0:D7
CCLK
WRITE
BUSY
CS
PROGRAM
DONE
M1 M2
Spartan-IIE
GND
INIT
DS077-2_06_110102
Figure 26,
27