XC2V1000-4BG575I Xilinx Inc, XC2V1000-4BG575I Datasheet - Page 23

• Manufacturer Part Number: XC2V1000-4BG575I
• Description: FPGA Virtex-II™ Family 1M Gates 11520 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 575-Pin BGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V1000-4BG575I

• Package: 575BGA
• Family Name: Virtex-II™
• Device Logic Units: 11520
• Device System Gates: 1000000
• Number Of Registers: 10240
• Maximum Internal Frequency: 650 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 328
• Ram Bits: 737280
• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 1000000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure
ple configurations.
DS031-2 (v3.5) November 5, 2007
Product Specification
WCLK
A[3:0]
A[4]
WE
WCLK
D
Figure 18: Distributed SelectRAM (RAM16x1S)
A[3:0]
Figure 19: Single-Port Distributed SelectRAM
WE
18,
(SR)
(BX)
(BY)
D
Figure
4
(BY)
(SR)
R
4
4
4
RAM 16x1S
WE
CK
A[4:1]
WG[4:1]
WSG
19, and
WS
RAM 32x1S
RAM
WE0
WE
CK
G[4:1]
WG[4:1]
F[4:1]
WF[4:1]
WSF
WS
WS
WSG
RAM
(RAM32x1S)
RAM
DI
Figure 20
D
DI
DI
D
D
F5MUX
(optional)
illustrate various exam-
D
Q
(optional)
D Q
DS031_02_100900
Output
Registered
Output
DS031_03_110100
Registered
Output
Output
www.xilinx.com
Similar to the RAM configuration, each function generator
(LUT) can implement a 16 x 1-bit ROM. Five configurations
are
ROM128x1, and ROM256x1. The ROM elements are cas-
cadable to implement wider or/and deeper ROM. ROM con-
tents are loaded at configuration.
number of LUTs occupied by each configuration.
Table 10: ROM Configuration
DPRA[3:0]
Figure 20: Dual-Port Distributed SelectRAM
available:
Virtex-II Platform FPGAs: Functional Description
WCLK
A[3:0]
A[3:0]
WE
128 x 1
256 x 1
D
16 x 1
32 x 1
64 x 1
ROM
(SR)
(BY)
4
ROM16x1,
4
4
(RAM16x1D)
RAM 16x1D
WE
CK
WE
CK
G[4:1]
WG[4:1]
G[4:1]
WG[4:1]
WSG
WSG
WS
WS
dual_port
RAM
dual_port
RAM
ROM32x1,
DI
DI
Number of LUTs
D
D
Table 10
16 (2 CLBs)
8 (1 CLB)
DS031_04_110100
1
2
4
Module 2 of 4
shows the
ROM64x1,
SPO
DPO
15