XC2V1000-4FF896I Xilinx Inc, XC2V1000-4FF896I Datasheet - Page 15

• Manufacturer Part Number: XC2V1000-4FF896I
• Description: FPGA Virtex-II™ Family 1M Gates 11520 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 896-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V1000-4FF896I

• Package: 896FCBGA
• Family Name: Virtex-II™
• Device Logic Units: 11520
• Device System Gates: 1000000
• Number Of Registers: 10240
• Maximum Internal Frequency: 650 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 432
• Ram Bits: 737280
• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 432
• Number Of Gates: 1000000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 896-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 5: Summary of Voltage Supply Requirements for
All Input and Output Standards
DS031-2 (v3.5) November 5, 2007
Product Specification
I/O Standard
LVDS_33
LVDSEXT_33
LVPECL_33
SSTL3_I
SSTL3_II
AGP
LVTTL
LVCMOS33
LVDCI_33
LVDCI_DV2_33
PCI33_3
PCI66_3
PCIX
SSTL3_I_DCI
SSTL3_II_DCI
LVDS_25
LVDSEXT_25
LDT_25
ULVDS_25
BLVDS_25
SSTL2_I
SSTL2_II
LVCMOS25
LVDCI_25
LVDCI_DV2_25
LVDS_25_DCI
LVDSEXT_25_DC
I
SSTL2_I_DCI
SSTL2_II_DCI
R
Output
3.3
2.5
V
CCO
Input
N/R
N/R
3.3
2.5
N/R
Input
V
1.32
1.25
1.25
1.25
1.25
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
1.5
1.5
1.5
1.5
REF
(1)
Output
Termination Type
Series
Series
Series
Series
Split
Split
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
Input
Split
Split
Split
Split
Split
Split
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
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Table 5: Summary of Voltage Supply Requirements for
All Input and Output Standards (Continued)
Notes:
1.
I/O Standard
HSTL_III_18
HSTL_IV_18
HSTL_I_18
HSTL_II_18
SSTL18_I
SSTL18_II
LVCMOS18
LVDCI_18
LVDCI_DV2_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
HSTL_I_DCI_18
HSTL_II_DCI_18
SSTL18_I_DCI
SSTL18_II_DCI
HSTL_III
HSTL_IV
HSTL_I
HSTL_II
LVCMOS15
LVDCI_15
LVDCI_DV2_15
GTLP_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI
HSTL_II_DCI
GTL_DCI
GTLP
GTL
N/R = no requirement.
Virtex-II Platform FPGAs: Functional Description
Output
N/R
1.8
1.5
1.2
V
CCO
Input
N/R
N/R
N/R
1.8
1.5
1.2
Input
V
0.75
0.75
0.75
0.75
N/R
N/R
N/R
N/R
N/R
N/R
1.1
1.1
0.9
0.9
0.9
0.9
1.1
1.1
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.8
0.8
REF
1
1
Output
Termination Type
Series
Series
Single
Series
Series
Single
Single
Single
Split
Split
Split
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
Module 2 of 4
Single
Single
Single
Single
Single
Single
Input
Split
Split
Split
Split
Split
Split
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
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