XC2V500-6FG456C Xilinx Inc, XC2V500-6FG456C Datasheet - Page 34

• Manufacturer Part Number: XC2V500-6FG456C
• Description: FPGA Virtex-II™ Family 500K Gates 6912 Cells 820MHz 0.15um/0.12um (CMOS) Technology 1.5V 456-Pin FBGA
• Manufacturer: Xilinx Inc

Specifications of XC2V500-6FG456C

• Package: 456FBGA
• Family Name: Virtex-II™
• Device Logic Units: 6912
• Device System Gates: 500000
• Number Of Registers: 6144
• Maximum Internal Frequency: 820 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 264
• Ram Bits: 589824

Each SelectRAM memory and multiplier block is tied to four
switch matrices, as shown in
Association With Block SelectRAM Memory
The interconnect is designed to allow SelectRAM memory
and multiplier blocks to be used at the same time, but some
interconnect is shared between the SelectRAM and the
multiplier. Thus, SelectRAM memory can be used only up to
18 bits wide when the multiplier is used, because the multi-
plier shares inputs with the upper data bits of the
SelectRAM memory.
This sharing of the interconnect is optimized for an
18-bit-wide block SelectRAM resource feeding the multi-
plier. The use of SelectRAM memory and the multiplier with
an accumulator in LUTs allows for implementation of a digi-
tal signal processor (DSP) multiplier-accumulator (MAC)
function, which is commonly used in finite and infinite
impulse response (FIR and IIR) digital filters.
DS031-2 (v3.5) November 5, 2007
Product Specification
Figure 35: SelectRAM and Multiplier Blocks
Switch
Switch
Switch
Switch
Matrix
Matrix
Matrix
Matrix
R
18-Kbit block
SelectRAM
Figure
35.
DS031_33_101000
www.xilinx.com
Configuration
The multiplier block is an 18-bit by 18-bit signed multiplier
(2's complement). Both A and B are 18-bit-wide inputs, and
the output is 36 bits.
Locations / Organization
Multiplier organization is identical to the 18 Kbit SelectRAM
organization, because each multiplier is associated with an
18 Kbit block SelectRAM resource.
In addition to the built-in multiplier blocks, the CLB elements
have dedicated logic to implement efficient multipliers in
logic. (Refer to
Table 20: Multiplier Floor Plan
A[17:0]
B[17:0]
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
XC2V250
XC2V500
XC2V40
XC2V80
Device
Virtex-II Platform FPGAs: Functional Description
Configurable Logic Blocks
Figure 36: Multiplier Block
Columns
Figure 36
2
2
4
4
4
4
4
6
6
6
6
MULT 18 x 18
Multiplier Block
shows a multiplier block.
Per Column
10
12
14
16
20
24
28
2
4
6
8
Multipliers
DS031_40_100400
(CLBs)).
Module 2 of 4
Total
120
144
168
24
32
40
48
56
96
P[35:0]
4
8
26