XC3S500E-4PQ208C Xilinx Inc, XC3S500E-4PQ208C Datasheet - Page 233

• Manufacturer Part Number: XC3S500E-4PQ208C
• Description: FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP
• Manufacturer: Xilinx Inc

Specifications of XC3S500E-4PQ208C

• Package: 208PQFP
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 158
• Ram Bits: 368640

Revision History
The following table shows the revision history for this document.
DS312-4 (v3.8) August 26, 2009
Product Specification
03/01/05
03/21/05
11/23/05
03/22/06
05/19/06
11/09/06
03/16/07
05/29/07
04/18/08
08/26/09
Date
R
Version
1.0
1.1
2.0
3.0
3.1
3.4
3.5
3.6
3.7
3.8
Initial Xilinx release.
Added XC3S250E in the CP132 package to
pairs on CP132. Added pinout and footprint information for the CP132, FG400, and FG484
packages. Removed IRDY and TRDY pins from the VQ100, TQ144, and PQ208 packages.
Corrected title of
the FG400 package, affecting
assignment were not affected. Added
package mass values to
Included I/O pins, not just input-only pins under the VREF description in
that some global clock inputs are Input-only pins in
XC3S100E in the CP132 package, affecting
Table
not an Input-only pin. Corrected the I/O counts for the XC3S1600E in the FG320 package,
affecting
XC3S1600E balls N14 and N15 in
Minor text edits.
Added package thermal data for the XC3S100E in the CP132 package to
Corrected pin migration arrows for balls E17 and F4 between the XC3S500E and
XC3S1600E in
modules to v3.4.
Minor formatting changes.
Corrected "Lxx" to "Lxxy" in
INPUT pins in
Data Sheets.
Added XC3S500E VQG100 package. Added Material Declaration Data Sheet links in
Table
Minor typographical updates.
136, and
127. Updated Thermal Characteristics in
Table
Table 124
129,
Figure
Table
Table
Table
151. Promoted Module 4 to Production status. Synchronized all
82. Ball A12 on the XC3S1600E in the FG320 package a full I/O pin,
www.xilinx.com
153. Updated differential pair numbering for some pins in Bank 0 of
and
Table
150,
Table
Table
Table 152
125.
Table
124. Noted that some GCLK and VREF pins are on
129. Added link before
Table
151, and
Package Thermal Characteristics
Revision
and
148.
Table
Table
Figure
Figure
Table
129. Corrected number of differential I/O
129,
Table
88. Pin functionality and ball
130. Updated links.
87. Corrected pin type for
Table
Table 127
124. Added information on the
130,
Table
to Material Declaration
Pinout Descriptions
Table
133,
Table
section. Added
124. Clarified
Table
130.
134,
233