MAX2538ETI+T Maxim Integrated Products, MAX2538ETI+T Datasheet - Page 8

• Manufacturer Part Number: MAX2538ETI+T
• Description: RF Mixer IC LNA/MIXER CELL/PCS/GPS
• Manufacturer: Maxim Integrated Products

Specifications of MAX2538ETI+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Quadruple-Mode PCS/Cellular/GPS LNA/Mixers
8
MAX2351
MAX2358
10, 20, 21
6, 8
_______________________________________________________________________________________
11
12
13
14
15
—
—
—
1
2
3
4
5
7
9
MAX2354 MAX2359
21, 25, 28
10, 20,
2, 6, 8
3, 27
11
12
13
14
15
—
—
—
—
1
4
5
7
9
1, 4, 6, 8,
10, 20,
21, 27
PIN
24
11
12
13
14
15
—
—
—
—
—
2
3
5
7
9
MAX2530
MAX2531
MAX2538
10
11
12
13
14
15
—
—
1
2
3
4
5
6
7
8
9
MAX2537
25, 28
10
11
12
13
14
15
—
1
3
4
5
2
6
7
8
9
GLNA_OUT
CLNA_OUT
N.C./GND
CLNA_IN
GLNA_IN
PLNA_IN
GMIX_IN
BUFFEN
NAME
MODE
SHDN
LO_IN
GND
BIAS
PLL
I.C.
G1
G2
Cellular LNA Output. Internally matched to 50Ω including an
on-chip DC-blocking capacitor.
PCS LNA Input. Requires a DC-blocking capacitor that can be
used as part of the matching network.
Ground
Cellular LNA Input. Requires a DC-blocking capacitor that can
be used as part of the matching network.
Shutdown Logic Input. A logic low shuts off the device, except
LO_OUT and PLL buffers, which are controlled by BUFFEN
and PLL pins, respectively.
Pin can be grounded or left open-circuit.
GPS LNA Input. Requires a DC-blocking capacitor, which can
be used as part of the matching network.
Operating Mode Logic Input. Sets device operating modes.
See Table 2 for details.
GPS LNA Output. Internally matched to 50Ω including an on-
chip DC-blocking capacitor.
Operating Mode Logic Input. Sets device operating modes.
See Table 2 for details.
Internally Connected. Do not make connections to this pin.
GPS Mixer Input. Requires a DC-blocking capacitor, which
can be used as an interstage coupling capacitor.
Operating Mode Logic Input. Sets device operating modes.
See Table 2 for details.
Bias Setting Pin. For nominal bias, connect a 20kΩ resistor to
ground. Adjust R
LNAs.
Dual-Function Pin. LO buffer output port for driving an external
PLL synthesizer. A logic high (through a 10kΩ resistor)
enables the PLL buffer. A logic low disables the PLL buffer.
Leave open if not used. If open, PLL is low.
LO Input. Internally matched to 50Ω, including DC-blocking
capacitor.
LO Buffer Enable Logic Input. A logic high enables the
external LO buffer port. Floats low.
BIAS
to alter the linearity of the mixers and
FUNCTION
Pin Description