MAX2831ETM+T Maxim Integrated Products, MAX2831ETM+T Datasheet - Page 20

• Manufacturer Part Number: MAX2831ETM+T
• Description: RF Transceiver 2.4GHz to 2.5GHz, 80 2.11g RF Transceiver
• Manufacturer: Maxim Integrated Products

Specifications of MAX2831ETM+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.4GHz to 2.5GHz 802.11g/b
RF Transceivers with Integrated PA
20
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PIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
1
2
3
4
5
6
7
8
9
GNDRXLNA
CLOCKOUT
GNDVCO
V
V
V
BYPASS
V
V
GNDCP
V
CPOUT
CTUNE
RXRF+
TXRF+
V
NAME
RXRF-
V
CCTXMX
TXRF-
SHDN
CCTXPA
CCXTAL
SCLK
TUNE
CCVCO
CCLNA
XTAL
RSSI
CCPLL
CCPA
DIN
CCCP
CS
B6
B7
B3
B2
B5
LD
B1
B4
LNA Supply Voltage
LNA Ground
Receiver and Transmitter Gain-Control Logic-Input Bit 6
LNA Differential Input. Input is internally AC-coupled and matched to 100Ω differential. Connect
directly to a 2:1 balun.
Receiver Gain-Control Logic-Input Bit 7
Supply Voltage for Second Stage of Power Amplifier
Receiver and Transmitter Gain-Control Logic-Input Bit 3
Power-Amplifier Differential Output for the MAX2831. PA output must be AC-coupled. PA driver
internally AC-coupled differential outputs and matched to 100Ω differential for the MAX2832. Connect
directly to a 2:1 balun.
Receiver and Transmitter Gain-Control Logic-Input Bit 2
Active-Low Shutdown and Standby Logic Input. See Table 31 for operating modes.
Supply Voltage for First-Stage of PA and PA Driver
Receiver and Transmitter Gain-Control Logic-Input Bit 5
Active-Low Chip-Select Logic Input of 3-Wire Serial Interface (See Figure 2)
RSSI, PA Power Detector (MAX2831 Only) or Temperature-Sensor Multiplexed Analog Output
Transmitter Upconverter Supply Voltage
Serial-Clock Logic Input of 3-Wire Serial Interface (See Figure 2)
Data Logic Input of 3-Wire Serial Interface (See Figure 2)
PLL and Registers Supply Voltage. Connect to the supply voltage to retain the register settings.
Reference Clock Buffer Output
Lock- D etect Log i c Outp ut of Fr eq uency S ynthesi zer . O utp ut hi g h i nd i cates that the fr eq uency synthesi zer
i s l ocked . O utp ut p r og r am m ab l e as C M OS or op en- d r ai n outp ut. ( S ee Tab l es 16 and 20.)
Receiver and Transmitter Gain-Control Logic-Input Bit 1
Charge-Pump Output. Connect the frequency synthesizer’s loop filter between CPOUT and TUNE
(see the Block Diagrams/Typical Operating Circuits).
PLL Charge-Pump Supply Voltage
Charge-Pump Circuit Ground
Crystal Oscillator Supply Voltage
Crystal or Reference Clock Input. AC-couple a crystal or a reference clock to this analog input.
Connection for Crystal Oscillator Off-Chip Capacitors. When using an external reference clock input,
leave CTUNE unconnected.
VCO Supply Voltage
VCO Ground
VCO TUNE Input (see the Block Diagrams/Typical Operating Circuits)
On-Chip VCO Regulator Output Bypass. Bypass with a 0.1µF to 1µF capacitor to GND. Do not
connect other circuitry to this point.
Receiver and Transmitter Gain-Control Logic-Input Bit 4
FUNCTION
Pin Description