MAX2112ETI+T Maxim Integrated Products, MAX2112ETI+T Datasheet - Page 9

• Manufacturer Part Number: MAX2112ETI+T
• Description: RF Receiver Direct Conversion Tu ner for DVB-S2 -40 t
• Manufacturer: Maxim Integrated Products

Specifications of MAX2112ETI+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1. Register Configuration
The MAX2112 includes 12 user-programmable regis-
ters and 2 read-only registers. See Table 1 for register
X = Don’t care.
NUMBER
REG
PIN
10
11
12
13
14
26
27
28
—
1
2
3
4
5
6
7
8
9
R EG I ST ER
Shutdown
N-Divider
N-Divider
R-Divider
F-Divider
F-Divider
Charge
Divider
Control
N A M E
Byte-1
Byte-2
Status
Status
Pump
XTAL
MSB
MSB
VCO
Test
LSB
LSB
PLL
LPF
NAME
ADDR
SDA
SCL
EP
_______________________________________________________________________________________
_______________________________________________________________________________________
WR IT E
R EA D /
Detailed Description
Read
Read
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
2-Wire Serial-Data Interface. Requires ≥ 1kΩ pullup resistor to V
2-Wire Serial-Clock Interface. Requires ≥ 1kΩ pullup resistor to V
Address. Must be connected to either ground (logic 0) or supply (logic 1).
Exposed Paddle. Solder evenly to the board’s ground plane for proper operation.
Register Description
A D D R ESS
0 = Set to 0 for factory-tested operation.
0x0A
0x0B
0x0C
0x0D
R EG
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
V C OS BR[4] V C OS BR[3] V C OS BR[2] V C OS BR[1] V C OS BR[0] AD C[ 2] AD C[ 1] AD C[ 0]
CPTST[2]
CPMP[1]
VCO[4]
LPF[7]
FRAC
XD[2]
Tuner for DVB-S2 Applications
STBY
F[15]
MSB
POR
D[7]
N[7]
F[7]
D24
X
1
0
0
Complete, Direct-Conversion
CPTST[1]
CPMP[0]
VCO[3]
LPF[6]
XD[1]
VASA
N[14]
F[14]
D[6]
N[6]
CPS
F[6]
PLL
X
0
0
0
configurations. The register configuration of Table 1
shows each bit name and the bit usage information for all
registers. Note that all registers must be written after and
no earlier than 100µs after the device is powered up.
CPTST[0]
CPLIN[1]
VCO[2]
LPF[5]
PWDN
XD[0]
N[13]
VASE
F[13]
FUNCTION
D[5]
N[5]
F[5]
ICP
DIV
0
0
0
0
Pin Description (continued)
DATA BYTE
CPLIN[0]
VCO[1]
LPF[4]
N[12]
F[12]
VCO
D[4]
N[4]
R[4]
F[4]
LD
X
X
X
1
0
CC
1 = Set to 1 for factory-tested operation.
CC
.
.
TURBO
VCO[0]
BBG[3]
LPF[3]
N[11]
F[19]
F[11]
D[3]
N[3]
R[3]
F[3]
BB
X
X
0
1
M U X[ 2]
LPF[2] LP F[ 1] LPF[0]
BBG[ 2] BBG[ 1] BBG[ 0]
RFMIX
N[10]
F[18]
F[10]
D[2]
N[2]
R[2]
VAS
F[2]
LD
X
0
X
0
RFVGA
M U X[ 1]
F[17]
D[1]
N[9]
N[1]
ADL
R[1]
F[9]
F[1]
LD
X
0
0
X
M U X[ 0]
LSB
F[16]
D[0]
ADE
N[8]
N[0]
R[0]
F[8]
F[0]
LD
FE
0
X
X
0
9
9