PI6C2502WEX Pericom Semiconductor, PI6C2502WEX Datasheet

PI6C2502WEX

Manufacturer Part Number

PI6C2502WEX

Description

Phase Locked Loops (PLL) 3.3v PLL Clock Drivr

Manufacturer

Pericom Semiconductor

Type

Zero Delay PLL Clock Driverr

Datasheet

1.PI6C2502WE.pdf (4 pages)

Specifications of PI6C2502WEX

Number Of Circuits

Supply Voltage (max)

3.6 V

Supply Voltage (min)

3 V

Maximum Operating Temperature

+ 70 C

Minimum Operating Temperature

0 C

Mounting Style

SMD/SMT

Operating Supply Voltage

3.3 V

Package / Case

SOIC-8

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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Product Features

• High-Performance Phase-Locked-Loop Clock Distribution

• Synchronous DRAM modules for server/workstation/

• Allows Clock Input to have Spread Spectrum

• Zero Input-to-Output delay

• Low jitter: Cycle-to-Cycle jitter ±100ps max.

• On-chip series damping resistor at clock output drivers

• Operates at 3.3V V

• Wide range of Clock Frequencies up to 80 MHz

• Package (Pb-Free & Green): Plastic 8-pin SOIC Package (W)

Logic Block Diagram

Figure 1. This Combination Provides Zero-Delay Between the

Reference

for Networking,

PC applications

modulation for EMI reduction

for low noise and EMI reduction

CLK_IN

FB_IN

Clock

Signal

08-0298

Reference Clocks Signal and 17 Outputs

Zero Delay

PI6C2502

Buffer

PLL

Feedback

CLK_OUT

Non-Zero

18 Output

Delay

Buffer

CLK_OUT

FB_OUT

Product Description

The PI6C2502 features a low-skew, low-jitter, phase-locked loop

(PLL) clock driver. By connecting the feedback FB_OUT output

to the feedback FB_IN input, the propagation delay from the

CLK_IN input to any clock output will be nearly zero.

Application

If a system designer needs more than 16 outputs with the features

just described, using two or more zero-delay buffers such as

PI6C2509Q, and PI6C2510Q, is likely to be impractical. The

device-to-device skew introduced can significantly reduce the

performance. Pericom recommends the use of a zero-delay buffer

and an eighteen output non-zero-delay buffer. As shown in Figure

1, this combination produces a zero-delay buffer with all the signal

characteristics of the original zero-delay buffer, but with as many

outputs as the non-zero-delay buffer part. For example, when

combined with an eighteen output non-zero delay buffer, a system

designer can create a seventeen-output zero-delay buffer.

Product Pin Configuration

CLK_OUT

FB_OUT

AGND

Phase-Locked Loop Clock Driver

8-Pin

CLK_IN

GND

FB_IN

PI6C2502

PS8382C

11/06/08

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PI6C2502WEX Summary of contents

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... N. 1st Street, San Jose, CA 95134 1-800-435-2335 • www.pericom.com DESCRIPTION: 8-Pin, 150-Mil Wide, SOIC PACKAGE CODE Pericom Semiconductor Corporation 4 Phase-Locked Loop Clock Driver DOCUMENT CONTROL NO 1001 REVISION: F DATE: 03/09/05 0.25 .0099 0.50 .0196 0.19 .0075 .0098 0.25 0.40 .016 1.27 .050 .2284 .2440 5.80 6. ...

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