MAX9987ETP-T Maxim Integrated Products, MAX9987ETP-T Datasheet - Page 9

• Manufacturer Part Number: MAX9987ETP-T
• Description: RF Amplifier +14dBm to +20dBm LO Buffers-Splitters wi
• Manufacturer: Maxim Integrated Products
• Type: LO Buffer/Splitterr

Specifications of MAX9987ETP-T

• Operating Supply Voltage: 5 V
• Supply Current: 221 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-20 EP
• Minimum Operating Temperature: - 40 C

The MAX9987/MAX9988 LO amplifiers/splitters each
consist of a single input amplifier, a two-way passive
power splitter, two separate output amplifiers, as well as
a third buffer amplifier to drive the LO’s PLL. The bias
currents for the amplifiers are adjustable through off-chip
resistors. This allows the output level to be precision set
anywhere from +14dBm to +20dBm. The PLL output is
preset to +3dBm (about 900mV
Power levels are typically ±1dB over the full supply, input
power, frequency, and temperature range. Precision
power control is achieved by internal control circuitry.
Maintaining tight power control keeps the system engi-
neer from over specifying the LO drive in order to guar-
antee a linearity specification in the base-station mixer.
More than 40dB isolation between the LO outputs and
the input prevents VCO pulling, and the 30dB output-
to-output isolation reduces branch-to-branch coupling.
The MAX9987 is specified from 700MHz to 1100MHz,
and the MAX9988 is specified from 1500MHz to
2200MHz. Both are offered in compact 5mm
pin QFN packages with exposed paddle.
1, 4, 8, 9, 13,
17, 18, EP
11, 12
14, 15
PIN
10
16
19
20
2
3
5
6
7
BIASOUT
VCCREF
OUTPLL
BIASIN
NAME
OUT2
VCC3
VCC2
OUT1
VCC1
GND
REF
_______________________________________________________________________________________
IN
+14dBm to +20dBm LO Buffers/Splitters
Detailed Description
Ground
Input. Internally matched 50 RF input. AC couple to this pin.
Supply. Supply connection for on-chip voltage and current references. See Applications Information
for information on decoupling.
Voltage Reference Output. Output for on-chip 1.5V bandgap voltage reference. See
Applications Information section for information on decoupling.
Bias Connection for Input Buffer. Set compressed power point for input amplifier with a resistor to
REF or GND. For +17dBm output power, no external biasing resistors are required. See Applications
Information section for information.
Bias Connection for Output Amplifiers. Set compressed power point for OUT1 and OUT2 with a
resistor to REF or ground. For +17dBm output power, no external biasing resistors are required. See
Applications Information section for information.
Output 2. Internally matched 50 RF output. AC couple to this pin.
Supply. Supply connection for OUT2.
Supply. Supply connection for OUT1.
Output 1. Internally matched 50 RF output. AC couple to this pin.
Supply. Supply connection for input amplifier.
Output PLL. Output for driving optional external PLL.
P-P
into 50Ω).
5mm 20-
A single low-noise input amplifier before the passive
splitter provides gain and isolation. The compressed
output power for this stage is controlled by the bias set-
ting resistors R
These resistors are not required for the nominal +17dBm
output; see Table 1 for bias resistor values to obtain
+14dBm to +20dBm output power.
The input is internally matched to 50Ω, and typical
VSWR is no more than 2:1 over all operating conditions.
Since the input is internally biased, provide a DC block
at the input pin.
A small amount of power is tapped off from the input
amplifier’s output, and fed to a high-isolation buffer to
drive the PLL output at +3dBm. If the PLL output is not
required, it can be disabled by removing R
the PLL output saves 12mA supply current.
The input amplifier drives an integrated power splitter.
All impedance matching between stages is on-chip, so
no external tuning components are required.
FUNCTION
with ±1dB Variation
1
or R
4
Passive Two-Way Splitter
(see Typical Application Circuit).
PLL Amplifier and Output
Pin Description
Input Amplifier
3
; disabling
9