ATA559001-DBW Atmel, ATA559001-DBW Datasheet - Page 53

• Manufacturer Part Number: ATA559001-DBW
• Description: RF Wireless Misc UHF (1kbit r/w anti- collis. Ni-Au)
• Manufacturer: Atmel

Specifications of ATA559001-DBW

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.1.1
8.1.2
8.1.3
4817C–RFID–03/07
Time-out Mechanism (Adaptive Watchdog Functionality)
Power Management During Forward Link
Resolution and Data Rate Management
During the following sections (data and EOF), the tag measures the time between two notch sig-
nals. Considering the timing of 0* and EOF*, the tag decides if it has received a binary 0, a
binary 1, or an EOF.
ATA5590 is based on an oscillator-based timing measurement. Therefore, the minimum symbol
length between two notches (edge-to-edge) is defined to be 5 oscillator clock cycles. Status2
register bit 3 indicates if the minimum length during the symbol transport was correct.
The oscillator frequency is tuned to 420 kHz (die) –10% to +40% at room temperature.
Based on the length of the first symbol of the header, ATA5590 adjusts the internal clock fre-
quency to save power. Therefore, the internal clock cycle can be half or double the internal
oscillator frequency.
Notes:
After receiving the second notch of the header section, an adaptive time-out mechanism is
enabled. During the header, ATA5590 stores the time between two notches. If there is no further
notch after 4 times this stored time, the forward link and the synchronous condition will both be
reset.
ATA5590 starts its timing measurement with the OSC frequency, and measures the time of the
first symbol (time between the first and the second notch of the header). If this time is lower than
an internal value, ATA5590 switches the internal clock to 2
consumption.
If the measured value is higher than a second internal value, ATA5590 switches to OSC / 2,
which results in lower power consumption.
The size of the internal timer is 8 bits. As explained before, by changing the timing of the first
symbol of the header, the internal frequency is changed. This has an effect on the timing mea-
surement unit which calculates the bits of the stream.
As this offers maximum flexibility, the timing is controlled by a hard-wired watchdog function,
which is given by a timer overflow condition (9th bit of the timer = timer overflow). If this occurs,
the link and the sync flag are reset. The data rate that is supported by ATA5590 is in the range of
5 Kbits/s to 60 Kbits/s.
• The time for a binary 0 is less than the time for 0*, for example 0.8 times 0*
• The time for a binary 1 is greater than for 0* but less than EOF*, for example 1.2 times 0*
• The time for an excepted EOF is greater than the time for EOF*, for example 1.2 times EOF*
• The resolution for timing checks can be changed under the control of the reader.
• The resolution and accuracy of the backscatter timing can be changed under the control of
• The data rate can be adapted.
the reader.
1. The time for a binary 1 must be less than for EOF*
2. The measurement is based on a timer measurement. The timer is driven by a clock signal. The
frequency of this clock signal depends on the adjustment of the first symbol of the header. It is
obvious that for comparison the difference between, for example, a logical 0 and 0* shall be
more then one clock cycle.
OSC. This increases the power
ATA5590
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