MAX2369EGM+TD Maxim Integrated Products, MAX2369EGM+TD Datasheet - Page 10

• Manufacturer Part Number: MAX2369EGM+TD
• Description: RF Transmitter Complete Dual-Band Q uadrature Transmitte
• Manufacturer: Maxim Integrated Products
• Type: Complete Dual-Band Quadrature Transmitterr

Specifications of MAX2369EGM+TD

• Package / Case: QFN-48
• Operating Frequency: 120 MHz to 235 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Noise Figure: - 145 dBm/Hz
• Operating Supply Voltage: 2.7 V to 3 V
• Supply Current: 80 mA to 155 mA
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Complete Dual-Band
Quadrature Transmitter
The IFM register sets the main frequency divide ratio
for the IF PLL. The IFR register sets the reference fre-
quency divide ratio. The IF VCO frequency can be
determined by the following:
where f
The operational control register (OPCTRL) controls the
state of the MAX2369. See
each bit.
The configuration register (CONFIG) sets the configura-
tion for the IF PLL and the baseband I/Q input levels
Table 1. Register Power-Up Default States
10
Figure 1. Register Configuration
REGISTER
OPCTRL
CONFIG
TEST
IFM
B19
IFR
______________________________________________________________________________________
MSB
X = DON’T CARE
X
X
X
X
X
REF
B18
X
X
X
X
X
IF VCO frequency = f
is the external reference frequency.
DEFAULT
B17
6519 dec
0492 dec
D03F hex
892F hex
0000 hex
X
X
X
X
X
B16
X
X
X
X
X
B15
B15
B15
X
X
X
ADDRESS
B14
B14
B14
0010
0011
0100
0101
0111
X
X
X
Table 3
REF
b
b
b
b
b
B13
B13
B13
B13
X
X
✕
B12
B12
B12
B12
X
X
IF M divider count
IF R divider count
Operational control
settings
Configuration and
setup control
Test-mode control
(IFM / IFR)
for the function of
B11
B11
B11
B11
FUNCTION
X
X
DATA 20 BITS
CONFIGURATION REGISTER (16 BITS)
B10
B10
B10
B10
B10
X
CONTROL REGISTER (16 BITS)
IFM DIVIDE RATIO REGISTER (14 BITS)
24 BIT REGISTER
B9
B9
B9
B9
B9
X
B8
B8
B8
B8
B8
X
IFR DIVIDE RATIO REGISTER (11 BITS)
B7
B7
B7
B7
B7
B7
See
The test register is not needed for normal use.
Bias control is distributed among several functional
sections and can be controlled to accommodate many
different power-down modes as shown in
The shutdown control bit is of particular interest since it
differs from the SHDN pin. When the shutdown control
bit is active (SHDN_BIT = 0), the serial interface is left
active so that the part can be turned on with the serial
bus while all other functions remain shut off. In contrast,
Table 2. Register Initialization for F
19.44MHz, F
F
REGISTER
COMP
OPCTRL
B6
B6
B6
B6
B6
B6
CONFIG
TEST
Table 4
IFM
IFR
TEST REGISTER (8 BITS)
B5
B5
B5
B5
B5
B5
= 360kHz
B4
B4
B4
B4
B4
B4
for a description of each bit.
DEFAULT
903D hex
1007 dec
0054 dec
890F hex
0000 hex
B3
B3
B3
B3
B3
B3
IF
= 181.26MHz,
B2
B2
B2
B2
B2
B2
B1
B1
B1
B1
B1
B1
ADDRESS
0010
0011
0100
0101
0111
B0
B0
B0
B0
B0
B0
b
b
b
b
b
A3
Power Management
0
0
0
0
0
ADDRESS 4 BITS
IF M divider count
IF R divider count
Operational control
settings
Configuration and
setup control
Test-mode control
A2
ADDRESS
ADDRESS
ADDRESS
ADDRESS
ADDRESS
0
0
1
1
1
FUNCTION
Table
A1
1
1
0
0
1
LSB
REF
A0
5.
0
1
0
1
1
=