ATA5823-PLQW Atmel, ATA5823-PLQW Datasheet
ATA5823-PLQW
Specifications of ATA5823-PLQW
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ATA5823-PLQW Summary of contents
Page 1
... ESD Protection at all Pins (±2.5 kV HBM, ±200V MM, ±500V FCDM) • Supply Voltage Range: 2.15V to 3.6V or 4.4V to 5.25V • Typical Power-down Current < • Temperature Range: –40°C to +105°C • Small QFN48 Package UHF ASK/FSK Transceiver ATA5823 ATA5824 4829D–RKE–06/06 ...
Page 2
... Manchester, Bi-phase and other codes in transparent mode. The ATA5824 can be used in the 433 MHz to 435 MHz band and the 867 MHz to 870 MHz band, the ATA5823 in the 313 MHz to 316 MHz band. The very high system integration level results in few numbers of external compo- nents needed ...
Page 3
... Pin Configuration Figure 2-1. Pinning QFN48 4829D–RKE–06/06 ATA5823/ATA5824 RF Transceiver Digital Control Logic XTO RF_IN 433_N868 6 ATA5823/ATA5824 NC 7 R_PWR 8 PWR_H 9 RF_OUT ATA5823/ATA5824 Power Supply Micro- controller Microcontroller interface RSSI CS 35 TEST3 34 33 SCK 32 SDI_TMDI SDO_TMDO 31 CLK 30 29 IRQ POUT 28 VSINT XTAL2 ...
Page 4
... TEST3 RSSI 37 CDEM 38 RX_TX2 39 RX_TX1 40 PWR_ON 41 NC ATA5823/ATA5824 4 Function Not connected Not connected Not connected RF input Not connected Selects RF input/output frequency range Not connected Resistor to adjust output power Pin to select output power RF output Not connected Not connected Not connected Not connected ...
Page 5
... FREF synthesizer Signal Processing (Mixer Synchronous logic IF-filter Demod_Out IF-amplifier FSK/ASK Demodulator, Data filter Data Slicer) GND ATA5823/ATA5824 DVCC Power Supply Switches Regulators TX/RX- Wake-up Data buffer Reset Control register Status register Polling circuit Bit-check logic (Full duplex operation mode) ...
Page 6
... Due to the single-ended and ground-referenced design, the loop antenna can be a free-form wire around the application usually employed in RKE unidirectional systems. The ATA5823/ATA5824 provides sufficient isolation and robust pulling behavior of internal circuits from the supply voltage as well as an integrated VCO inductor to allow this ...
Page 7
... OUT shows a typical 433.92 MHz supply blocking capacitor about 10 dBm Since a quarter wave or PCB antenna, OUT ATA5823/ATA5824 C 6 CDEM RSSI CS TEST3 SCK SDI_TMDI SDO_TMDO ATA5823/ATA5824 CLK IRQ POUT VSINT NC XTAL2 13.25311 MHz 4.4V to 5.25V CC = 4.4V to 5.25V RKE car application. The external 2.2 µ ...
Page 8
... Due to additional capacitive coupling between the loops the position of the components C The receive Sensitivity in full-duplex mode is reduced from –106 dBm without coupled RF-Power at RF_IN to –96 dBm with –35 dBm coupled RF power at RF_IN. ATA5823/ATA5824 RF_IN 433_N868 ATA5823/ATA5824 R_PWR L 2 PWR_H RF_OUT ...
Page 9
... RX-antenna to the SAW and the SAW typically 22 k and SETPWR is programmed to get an output 1 102 dBm with 45 dBm coupled RF power at RF_IN. The use of SAW fil- – – ATA5823/ATA5824 C 6 CDEM RSSI CS TEST3 SCK SDI_TMDI SDO_TMDO ATA5823/ATA5824 CLK IRQ C POUT 2 VSINT NC XTAL2 13.25311 MHz 4.4V to 5.25V ...
Page 10
... IF filter the receiver has a better selectivity and blocking performance than more complex double superhet receivers, without using external components and without numerous spurious receiving frequencies. Note: ATA5823/ATA5824 10 Figure 2-2 on page 5, the RF transceiver consists of an LNA (Low-Noise Amplifier), for exact values). The transmit data can also be buffered as described in section 35 ...
Page 11
... The reflection coefficients were always may be necessary to compensate individual 1 Table 7-3 on page 12 and Table 7-4 on page = and the matching loss with L 105.5 dBm to 106.7 dBm. The sensitivity also – – are based on the values of registers 5 and 6 ATA5823/ATA5824 4 RF_IN //C In_p and with 12. 11 ...
Page 12
... Measured Sensitivity 433.92 MHz/FSK/20 Kbit/s/±19.5 kHz/Manchester versus Frequency Offset, Tempera- ture and Supply Voltage -110 -109 -108 -107 -106 -105 -104 -103 -102 -101 -100 -99 -98 -97 -96 -95 -100 -80 ATA5823/ATA5824 12 Input Matching /MHz C / 315 2.4 433.92 1.8 868.3 1.2 BR_Range_0 BR_Range_1 2.4 Kbit/s 5.0 Kbit/s –110.0 dBm – ...
Page 13
... For the demodulator used in the ATA5823/ATA5824, the tolerable frequency offset does not change with the data frequency, hence, the value of ±75 kHz is valid for 1 Kbit Kbit/s. 35). ...
Page 14
... This system calculation is based on worst case tolerances of all the components, this leads in practice to a system with margin. For a 315 MHz TPM system using a TPM transmitter ATA5756 and a transceiver ATA5823 as receiver the same calculation must be done, but since the RF frequency is lower, every ppm of crystal tolerances results in less frequency offset and either the system can have higher toler- ances or a higher margin there ...
Page 15
... Distance of Interfering to Receiving Signal (MHz) Narrow Band 3 dB Blocking Characteristic at 433.92 MHz - Distance of Interfering to Receiving Signal (MHz) Wide Band 3 dB Blocking Characteristic at 433.92 MHz -10 -50 -40 -30 -20 -10 Distance of Interfering to Receiving Signal (MHz) ATA5823/ATA5824 0 0.2 0.4 0.6 0.8 1 ...
Page 16
... Table 7-6. The ATA5823/ATA5824 can also receive FSK and ASK modulated signals if they are much higher than the I1dBCP. It can typically receive useful signals at +10 dBm. This is often referred to as the nonlinear dynamic range which is the maximum to minimum receiving signal which is 115.5 dB for 433.92 MHz/FSK/20 Kbit/s/± ...
Page 17
... IF filter. Hence the demodulator, data filter and data slicer are important in that case. The data filter of the ATA5823/ATA5824 implies a quasi-peak detector. This results in a good suppression of above mentioned disturbers and exhibits a good carrier to noise performance. ...
Page 18
... MHz and 868 MHz ISM bands can be programmed as receive and as transmit frequency and the position of channels within these ISM bands can be chosen arbitrarily (see ATA5823/ATA5824 18 45 dBm and the gain is 8 mV/dB. – ...
Page 19
... Center 433.92 MHz Res BW 100 kHz 4829D–RKE–06/06 Figure 4-1. In ASK mode the frequency is internally connected to the center of the to Figure 7-11 on page 20 show the spectrum of the FSK modulation with Atten 20 dB VBW 100 kHz ATA5823/ATA5824 Span 30 MHz Sweep 7.5 ms (401 pts) 19 ...
Page 20
... Figure 7-11. FSK-modulated TX Spectrum (433.92 MHz/20 Kbit/s/±19.41 kHz/Manchester Code) Ref 10 dBm Samp Log 10 dB/ VAvg Center 433.92 MHz Res BW 10 kHz ATA5823/ATA5824 20 ) FSK_L Atten 20 dB VBW 10 kHz Atten 20 dB VBW 10 kHz Span 1 MHz Sweep 27.5 ms (401 pts) Span 1 MHz Sweep 27.5 ms (401 pts) ...
Page 21
... Table 7-7 on page 22 were measured with standard multi-layer chip inductors with Table 7-7 on page and the matching loss with 10 log ( “Electrical Characteristics: General” on page (10 nF ATA5823/ATA5824 22) sets a reference current which controls the The 1 Lopt , Table 7-7. Note that value changes of 10 ...
Page 22
... ATA5823/ATA5824 22 Table 12-25 on page 43. It can be used in conjunction with an external resistor that the output power should be adjusted with an external resistor about 50% AVCC RF OUT VPWR_H Output Power R1 ...
Page 23
... Measurements of Typical Output Power Relative to 3 V/25° 2.15V –40°C –3.0 dB amb = +25°C –2.8 dB amb = +105°C –3.2 dB ATA5823/ATA5824 Table 7-7 on page 2 0.4V) if the load impedance is not – /(2.15V 0.4V 3.4 dB. Table 7-8 – 3.0V 10.19 mA 5.5 dBm 11. ...
Page 24
... C tion). To keep the 50 impedance in RX mode at the end of this transmission line C also about 7.6 pF. This reduces the TX power by about 0 433.92 MHz compared to the case where the LNA path is completely disconnected. ATA5823/ATA5824 24 Table 7-10 on page 24 and ...
Page 25
... The RX and TX losses will be in the range of 1.0 dB there Transceiver in Full-duplex Mode The full-duplex mode of the ATA5823/ATA5824 is intended to be used for the purpose of secu- rity against a so called relay attack in passive entry systems. A property of such a passive entry system is that the user has not to push a key fob button like in a keyless entry system. If the user ...
Page 26
... To prevent that the ATA5823/ATA5824 receives and transmit its RF-signals on the same fre- quency and at the same time. Since the attacker has then to receive and transmit RF signals at the same frequency and time it will be much more difficult to built the hardware for this kind of attack, since its own transmitted output power couples back to its receiver ...
Page 27
... L the shunt and the total actual load capacitance of the crystal in the circuit and con- L and C in series connection ATA5823/ATA5824 = 22k, 1 3.0V 10.9 mA/–5.2 dBm 11.4 mA/–4.6 dBm 12.5 mA/–5.2 dBm 13.1 mA/–4.5 dBm 14.2 mA/–5.9 dBm 14.8 mA/–5.0 dBm = 22k, ...
Page 28
... After 10 High if the amplitude is large enough. This activates the CLK output if CLK_ON and CLK_EN in control register 3 are High (see the DVCC voltage also have to be fulfilled (see 31). ATA5823/ATA5824 28 XTAL with Load Capacitances XTAL fF ...
Page 29
... XTO Block Diagram XTAL1 XTAL2 f XTO the switches S1 and S2 are open. 39) the relationship between f so that f is exactly the desired radio frequency. RF ATA5823/ATA5824 29 7 CLK & DVCC_OK Divider (from power supply) /3 CLK_EN CLK_ON (control (control register 3) register 3) Amplitude XTO_OK ...
Page 30
... If bit CLK_ON is set to 1 and thus the clock is enabled if the Bit-check is ok (RX, RX Poll- ing, FD mode (Slave)), an event on pin N_PWR_ON occurs or the bit Power_On in the status register is 1. Figure 9-3. Clock Timing DVCC CLK CLK_EN (Control Register 3) CLK_ON (Control Register 3) ATA5823/ATA5824 30 f (MHz XTO RF TX_ASK RX ...
Page 31
... Table 12-16 on page BR_Range 0: T BR_Range 1: T BR_Range 2: T BR_Range OUT V_REG1 3.25V typ. EN FF1 change ATA5823/ATA5824 Table 12-19 on page 41) and X 40). This clock cycle T XDCLK = XDCLK DCLK Lim = XDCLK DCLK Lim = XDCLK DCLK Lim = XDCLK DCLK Lim SW_AVCC AVCC DVCC ...
Page 32
... The supply voltage range of the ATA5823/ATA5824 is 2.15V to 3.6V or 4.4V to 5.25V. Pin VS1 is the supply voltage input for the range 2.15V to 3.6V and is used in battery applica- tions using a single lithium 3V cell. Pin VS2 is the voltage input for the range 4.4V to 5.25V (car applications), in this case the voltage regulator V_REG regulates VS1 to typically 3.25V. If the voltage regulator is active, a blocking capacitor of 2.2 µ ...
Page 33
... The internal signal DVCC_RESET resets the digital control logic and exceeds 1.6V (typically) and the start-up time of the XTO is elapsed, the output DVCC drops below 1.6V (typically) and pin N_PWR_ON = 1 and pin PWR_ON = 0 the trans- ATA5823/ATA5824 Figure 3-1 on page 6 Figure 4-1 on page 7 and ...
Page 34
... Figure 10-5. Battery Application ATA5823/ATA5824 34 1.6V (typ) read status register V > 1.6V and the XTO is running DVCC CLK OFF mode IDLE mode IDLE, TX, RX, RX Polling, FD mode DVCC_OK XTO_OK ATA5823/ATA5824 VS1 VS2 RF transceiver AVCC Digital control logic DVCC VSINT CS SCK SDI_TMDI SDO_TMDO IRQ CLK OFF mode & ...
Page 35
... The microcontroller interface is a level converter which converts all internal digital signals which are referred to the DVCC voltage, into the voltage used by the microcontroller. Therefore, the pin VSINT can be connected to the supply voltage of the microcontroller in the case the microcon- troller has another supply voltage than the ATA5823/ATA5824. 12. Digital Control Logic 12.1 Register Structure The configuration of the transceiver is stored in RAM cells ...
Page 36
... FR12 FR11 ASK_ Sleep NFSK BitChk BitChk 1 Baud Baud 1 POUT_ POUT_ SELECT DATA FE_ - MODE N_ Power _On - = Don’t care ATA5823/ATA5824 36 PLL_ FS OPM2 OPM1 OPM0 MODE FR4 FR3 FR2 FR1 FR0 CLK_ FR10 FR9 FR8 FR7 EN Sleep Sleep Sleep Sleep XSleep ...
Page 37
... Control Register 1 (Function of Bit 5) Function 0 Adjustable range of FREQ: 3072 to 4095 (default), see 1 Adjustable range of FREQ 8191, see Control Register 1 (Function of Bit 4) Function (RX Mode, TX Mode, FD Mode) 0 Selected frequency 433/868 MHz (default) 1 Selected frequency 315 MHz ATA5823/ATA5824 Table 12-10 on page 39 Table 12-11 on page 39 37 ...
Page 38
... OPM2 Table 12-6. T_MODE 12.3.2 Control Register 2 (ADR 1) Table 12-7. FR6 Note: Table 12-8. P_MODE Table 12-9. P_MODE Note: ATA5823/ATA5824 38 Control Register 1 (Function of Bit 3, Bit 2 and Bit 1) OPM1 OPM0 Function 0 0 IDLE mode (default mode polling mode mode Full-duplex mode (Master ...
Page 39
... Clock output off (pin CLK). Clock switched event: - Bit-check event on pin N_PWR_ON or - bit Power_On in the status register Clock output on (default) Bit CLK_ON is set the Bit-check is ok (RX_Polling, RX mode), an event at pin N_PWR_ON occurs or the bit Power_On in the status register is 1. ATA5823/ATA5824 FR7 7 2 Function 0 FREQ3 = 3072 1 FREQ3 = 3200 ...
Page 40
... XSleep Note: Table 12-16. Control Register 4 (Function of Bit 0) XLim Note: 12.3.5 Control Register 5 (ADR 4) Table 12-17. Control Register 5 (Function of Bit 7 and Bit 6) BitChk1 Note: ATA5823/ATA5824 40 Function (TX Mode, RX Mode) 0 FSK mode (default) 1 ASK mode Bit ASK_NFSK has no function in FD mode Sleep1 Sleep0 ...
Page 41
... XDCLK DCLK Note that the receiver is not working with >10 Kbit/s in ASK mode Lim_max2 Lim_max1 Lim_max0 ATA5823/ATA5824 Function (RX Mode, FD Mode Slave) Lim_min (Lim_min < 10 are not Applicable Lim_min T Lim_min XDCLK Lim_min XDCLK (default Lim X Lim T ) DCLK X (default) Lim X Lim Function (RX Mode, FD Mode Slave) Lim_max (Lim_max < ...
Page 42
... Note: Bits TX0 to TX5 have no function in RX mode and FD mode 12.3.8 Control Register 8 (ADR 7) Table 12-23. Control Register 8 (Function of Bit 6) FE_mode Table 12-24. Control Register 8 (Function of Bit 5) PWSELECT ATA5823/ATA5824 42 POUT_DATA IDLE, TX, FD mode: N_RX_ACTIVE = 1 RX mode: N_RX_ACTIVE = 0 TX2 TX1 Function 0 For future use ...
Page 43
... DVCC_RST = 1 supply voltage of the RAM was too low (typically V If the transceiver changes from OFF mode to IDLE mode, DVCC_RST will be set to 1. Reading the Status register resets DVCC_RST to 0. ATA5823/ATA5824 Function (TX Mode, FD Mode) (SETPWR: Programmable internal resistor to reduce the output power ...
Page 44
... While the debounce counter is running, the bit CLK_ON in control register 3 is set to 1. The interrupt is deleted after reading the status register or executes the command Delete_IRQ. If pin N_PWR_ON is not used, it can be left open because of an internal pull-up resistor (typi- cally ATA5823/ATA5824 44 ) for at least T (see ...
Page 45
... Start debounce counter Event on pin N_PWR_ON ? N Y Stop debounce counter Stop debounce counter ) for at least T (see Figure 12-4 on page VSINT PWR_ON exceeds 1.6V (typically) and the XTO is settled, the digital control logic is active and ATA5823/ATA5824 T = 8195 T DCLK Pin N_PWR_ON Stop debounce counter N_Power_On = 1; ...
Page 46
... DVCC_RST The status bit DVCC_RST is set the voltage on pin DVCC V (typically). DVCC_RST is set 4-wire serial interface (see ATA5823/ATA5824 not possible to set the transceiver to OFF mode by setting pin PWR_ON pin PWR_ON is not used, it must be connected to GND. T > T PWR_ON PWR_ON_IRQ_1 1 ...
Page 47
... Command: Read TX/RX Data Buffer SDO_TMDO No. Bytes in the TX/RX Data Buffer SCK CS 4829D–RKE–06/06 IDLE, TX Polling Mode, FD Mode VDVCC < 1.6V (typ Pin PWR_ON = 1 or pin N_PWR_ON = DVCC_RST = 1; Read Status Register LSB MSB LSB MSB X RX Data Byte 1 ATA5823/ATA5824 OFF_Mode LSB X RX Data Byte 1 47 ...
Page 48
... Command: Write Control Register The control registers can be written individually or successively. Figure 13-4. Write Control Register MSB SDI_TMDI Command: Write Control Register X SDO_TMDO No. Bytes in the TX/RX Data Buffer SCK CS ATA5823/ATA5824 48 LSB MSB LSB MSB TX Data Byte 1 Write TX/RX Data Buffer LSB MSB ...
Page 49
... TX buffer. This means that and have the same function. In all other commands Bit 0 to Bit 4 have no effect and should be set to 0 for compatibility rea- sons with future products. 4829D–RKE–06/06 ATA5823/ATA5824 MSB LSB SDI_TMDI Command: OFF Command SDO_TMDO No ...
Page 50
... When CS is inactive and the transceiver is not in RX transparent mode, SDO_TMDO high-impedance state. Pins SCK_POL and SCK_PHA defines the polarity and the phase of the serial clock SCK. Figure 13-7. Serial Timing SCK_POL = 0, SCK_PHA = 0 SDI_TMDI SDO_TMDO ATA5823/ATA5824 50 Command Structure MSB Bit 7 Bit 6 ...
Page 51
... T T CS_setup Cycle T Hold T Setup MSB X MSB Out_enable Out_delay MSB CS_setup Cycle T T Setup Hold X MSB X T Out_delay X MSB ATA5823/ATA5824 T CS_disable T CS_setup2 T SCK_hold X MSB-1 LSB X T Out_disable MSB-1 LSB T CS_disable T SCK_setup2 T SCK_hold Out_disable MSB-1 LSB T CS_disable T CS_setup2 T SCK_hold X MSB-1 LSB X T Out_disable ...
Page 52
... T tistical process. An average value for T T Startup_PLL consumption is I RX_ACTIVE (see ferent in battery application or car application. To calculate I VS1,2 in battery application or VS2 in car application (see section General” on page -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Poll ATA5823/ATA5824 52 Control Register 1 OPM1 OPM0 During the start-up period ...
Page 53
... Sleep the PLL is enabled and starts up. If the PLL is locked, the signal processing Startup_PLL ). After the start-up time all circuits are in stable condition and Startup_Sig_Proc ATA5823/ATA5824 . If CLK is enabled during the RX polling mode VSINT the transceiver is not sensitive to a transmitter sig- Preburst and T ...
Page 54
... The incomming data stream is passed via the TX/RX Data Buffer or via pin SDO_TMDO to the connected microcontroller bit error occurs the transceiver is set back to Start-up mode. Output level on pin RX_ACTIVE -> High RX_X Start bit detected ? YES RX data stream is written into the TX/RX Data Buffer Bit error ? YES ATA5823/ATA5824 IDLE_X X Sleep = Startup_PLL_X Startup_PLL = RX_X ...
Page 55
... Bit-check is defined by two separate time lim between the lower Bit-check limit the check will be continued Lim_max , the Bit-check will be terminated and the transceiver switches to sleep mode. Demod_Out ATA5823/ATA5824 Bit-check Bit-check 1/2 Bit 1/2 Bit 1/2 Bit Receiving mode ...
Page 56
... CV_Lim reaches Lim_max. This is illustrated in Figure 14-4. Timing Diagram During Bit-check (Lim_min = 14, Lim_max = 24) RX_ACTIVE Bit-check Demod_Out Bit-check counter 0 T Startup_Sig_Proc Start-up mode ATA5823/ATA5824 time window of ±38%. To get the maximum sensitivity the and T . The time resolution defining T Lim_max XDCLK is defined according to the section ee ...
Page 57
... Bit_check Bit-check mode is given in the electrical characteristics. T Bit-check XDCLK resulting in a lower current consumption in RX polling mode. , and the count of the bits, N Bit-check requiring a higher value for the transmitter pre-burst T Bit-check ATA5823/ATA5824 0 T Sleep Sleep mode Lim_max Sleep Sleep mode varies for each check. There- ...
Page 58
... The start bit is part of the first data byte and must be different from the bits of the preburst. If the preburst consists of a sequence of “00000...”, the start bit must the preburst consists of a sequence of “11111...”, the start bit must ATA5823/ATA5824 58 '0' ...
Page 59
... Logical error (no edge detected in the bit center) The byte consisting of the bit error will not be stored in the TX/RX data buffer. Thus it is not avail- able via the 4-wire serial interface. Start-up mode Bit-check mode ATA5823/ATA5824 47 byte is trans- Byte 16, Byte 32, ... Byte 15, Byte 31, ... ...
Page 60
... Kbit BR_Range_0 RF XTAL MHz XLim = 1 315 Lim_min = 13 (251 µs) (12.73193) Lim_max = 38 (715 µs) 433.92 Lim_min = 13 (251 µs) (13.25311) Lim_max = 38 (715 µs) 868.3 Lim_min = 13 (248 µs) (13.41191) Lim_max = 38 (706 µs) ATA5823/ATA5824 60 RX Demodulation Scheme ASK/_NFSK T_MODE ASK 0 f ASK have been done with the Lim_min and Lim_max values according to 2 ...
Page 61
... Table 9-1 on page 47 byte is loaded, the counter is incremented byte is transmit- Writing to the control register during TX mode, resets the TX/RX data buffer and the counter which indicates the number of bytes to be transmitted. illustrates the flow chart of the TX transparent mode. ATA5823/ATA5824 OPM0 Function 1 TX mode 62. The bit rate depends on Baud0 and Baud1 in “ ...
Page 62
... Figure 14-10. TX Operation (T_MODE = 0) Command: Delete_IRQ N Pin IRQ = Write Control Register 1 OPM2, OPM1, OPM0: ATA5823/ATA5824 62 Write Control Register 8 FE_MODE: PWSELECT: PWSET0 to PWSET4: Write Control Register 7 POUT_SELECT, POUT_DATA: TX0 to TX5: Write Control Register 6 Baud1, BAUD0: Lim_max0 to Lim_max5: Write Control Register 5 Bit_ck1, Bit_ck0: ...
Page 63
... Don’t care Adjust RF Application defined. Adjust RF Don’t care Don’t care Set PLL_MODE = 0 Select operation frequency Set OPM2 = 0, OPM1 = 0 and OPM0 = 1 Set T_mode = 0 Apply TX Data on Pin SDI_TMDI Set IDLE ATA5823/ATA5824 Idle Mode Start-up Mode (TX 331.5 T Startup DCLK TX Mode Idle Mode 63 ...
Page 64
... In the slave the TX data stream consists of the synchronization pattern (3 bytes) and also maxi- mally 8 bytes of data. The synchronization pattern contains 3 bytes with a fixed value (Byte1: 00 hex, Byte2: 7F hex, Byte3: FF hex). The data block is user defined and contains maximally 8 bytes slave. ATA5823/ATA5824 64 Bit in TX/RX P_Mode T_Mode ...
Page 65
... MSB LSB Start bit 3 Bytes Synchronization Pattern 8 Bytes Data ATA5823/ATA5824 49). TX Buffer Slave MSB LSB Synchronization Byte 1 (00 hex Synchronization Byte 2 (7F hex Synchronization Byte 3 (FF hex Data Byte Data Byte Data Byte Data Byte Data Byte Data Byte Data Byte 7 ...
Page 66
... For a proper operation in the slave, a wake-up due to noise must be prevent (bit check + start bit ok). To achieve this for the slave the following adjustments are recommended: 1. Set N 2. Start FD mode in master and slave as simultaneously as possible. ATA5823/ATA5824 66 depends on the preburst length and the number of bits to be checked FD_sync < ...
Page 67
... IDLE Mode t 4829D–RKE–06/06 T FD_sync PA enabled and at least N Byte in TX Buffer T Bitcheck_min At least N Byte in TX Buffer Master and Slave synchron Pin IRQ = 1; PA disabled Pin IRQ = 1; PA disabled ATA5823/ATA5824 Slave Enable FD Mode Startup (T = 798 Startup_PLL_fd DCLK Startup Analog Signal Processing (T ...
Page 68
... Write Control Register 1 IR1, IR0: PLL_MODE: FS: OPM2, OPM1, OPM0: T_MODE: (Preburst startbit synchronization pattern, data block) Write Control Register 1 OPM2, OPM1, OPM0: ATA5823/ATA5824 68 Set FE_MODE = 1 Don’t care Adjust SETPWR to reduce the output power Application defined Don’t care BAUD1 = 0, BAUD0 = 1 Don’ ...
Page 69
... Don’t care Application defined Select operating frequency Set OPM2 = 1, OPM1 = 1 OPM0 = 1 T_MODE = 0 Write TX/ RX Buffer (Synchronization pattern, data block) (max. 9 byte) N Pin IRQ = Read TX/ RX Buffer Set IDLE ATA5823/ATA5824 Idle Mode Start-up FD Mode (Slave 798.5 T Startup_PLL_fd DCLK T = 546 T Startup_sig_proc_fd DCLK FD Mode ...
Page 70
... IR0 and IR1 in control register 1) Successful Bit-check (P_MODE = 0) Events During FD Operation TX data buffer empty Note: ATA5823/ATA5824 70 Interrupt Handling to High Level 0) 1. During reading of the RX/TX buffer, no IRQ is issued, due to the received bytes or a receiv- ing error. ...
Page 71
... Symbol Min –55 stg T –40 amb V –0.3 MaxVS2 V –0.3 MaxVS1 V –0.3 MaxVSINT HBM –2.5 MM –200 FCDM –500 P in_max Symbol Value R 25 thJA ATA5823/ATA5824 Max. Unit 150 °C +125 °C +105 °C +7 +5.5 V +2.5 kV +200 V 500 V 10 dBm Unit K/W 71 ...
Page 72
... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to page 22 with component values according to ATA5823/ATA5824 72 = –40°C to +105°C, V amb VS1 (1) Pin 4, 10 ...
Page 73
... REF1 = 19.5 kHz DEV kHz kHz ( REF_ASK REF1 + S + REF_FSK REF1 Table 7-2 on page 12 (RF ) and RF_OUT matched to 50 according to IN Table 7-7 on page 22 ATA5823/ATA5824 = 2.15V to 3.6V (battery application), and VS2 VSINT = and T VS1 VS2 VSINT Min. Typ. I 10.5 S_RX I 10.3 S_RX ...
Page 74
... RF *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to page 22 with component values according to ATA5823/ATA5824 74 = –40°C to +105°C, V amb VS1 (1) Pin (4), 36 ...
Page 75
... P = ±19.5 kHz (4) P DEV (4) (4) (4) (4) (4) (4) (4) (4) Table 7-2 on page 12 (RF ) and RF_OUT matched to 50 according to IN Table 7-7 on page 22 ATA5823/ATA5824 = V = 2.15V to 3.6V (battery application), and VS2 VSINT = and T VS1 VS2 VSINT Min. Typ. Max. SBW 220 IIP2 +50 IIP3 –22 IIP3 – ...
Page 76
... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to page 22 with component values according to ATA5823/ATA5824 76 = –40°C to +105° amb VS1 (1) Pin Symbol ...
Page 77
... Lopt f 1 17, 18, I S_TX_PAON1 27 17, 18, I S_TX_PAON1 27 17, 18, I S_TX_PAON1 27 Table 7-2 on page 12 (RF ) and RF_OUT matched to 50 according to IN Table 7-7 on page 22 ATA5823/ATA5824 = 2.15V to 3.6V (battery application), and VS2 VSINT = and T VS1 VS2 VSINT Symbol Min. Typ BLOCK 64 67 – ...
Page 78
... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to page 22 with component values according to ATA5823/ATA5824 78 = –40°C to +105°C, V amb VS1 (1) Pin ...
Page 79
... (10) (10) (10) = 433.92 MHz 17,18 17,18 17,18, 27 Table 7-2 on page 12 (RF ) and RF_OUT matched to 50 according to IN Table 7-7 on page 22 ATA5823/ATA5824 = 2.15V to 3.6V (battery application), and VS2 VSINT = and T VS1 VS2 VSINT Symbol Min. Typ. 15.7 15.8 17.3 P –0.8 REF P REF ...
Page 80
... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to page 22 with component values according to ATA5823/ATA5824 80 = –40°C to +105°C, V amb VS1 (1) Pin ...
Page 81
... P REFTX_FD4 REFTX_FD4 = V = 2.15V to 3.6V VS2 = –40°C to 105° (10 REFTX_FD4 REFTX_FD4 Table 7-2 on page 12 (RF ) and RF_OUT matched to 50 according to IN Table 7-7 on page 22 ATA5823/ATA5824 = 2.15V to 3.6V (battery application), and VS2 VSINT = and T VS1 VS2 VSINT Symbol Min. Typ. P –2.5 – ...
Page 82
... RF *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to page 22 with component values according to ATA5823/ATA5824 82 = –40°C to +105°C, V amb VS1 (1) Pin = resonant frequency of 24 ...
Page 83
... SETPWR = 800 + SETPWR PWSET = 16 Table 12-25 on page 43) 19 SETPWRTOL , CLK enabled Table 7-2 on page 12 (RF ) and RF_OUT matched to 50 according to IN Table 7-7 on page 22 ATA5823/ATA5824 = 2.15V to 3.6V (battery application), and VS2 VSINT = and T VS1 VS2 VSINT Symbol Min. Typ. f XTO ...
Page 84
... MHz RF *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 according to component values according to page 22 with component values according to ATA5823/ATA5824 84 = –40°C to +105° amb VS1 (1) Pin ...
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... VSINT VSINT 27 I VSINT 30 CLK Table 7-2 on page 12 (RF ) and RF_OUT matched to 50 according to IN Table 7-7 on page 22 ATA5823/ATA5824 = V = 2.15V to 3.6V (battery application), and VS2 VSINT = and T VS1 VS2 VSINT Min. Typ. Max. 5 (4.8 + j3.2) (4.5 + j4. j9) 2 ...
Page 86
... Current in 10.10 RX polling mode on pin VS1 and VS2 Supply current 10.11 RX polling mode *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA5823/ATA5824 86 = –40°C to +105°C, V amb VS1 Figure 3-1 on page 6 or Figure 5-1 on page has to be added. ...
Page 87
... R_PWR I FD2_VS1_VS2 18 dBm out = V 3V VS1 VS2 = 22 k 17, R_PWR I FD3_VS1_VS2 18, 27 17, 18, 27 ATA5823/ATA5824 = V = 2.15V to 3.6V typical values at V VS2 315.0 MHz/ 433.92 MHz/868.3 MHz unless RF Min. Typ. Max. 10.3 13.4 15.7 20.5 10.5 13.5 15.8 20.5 11.2 14.5 17.3 22 ...
Page 88
... MHz/5dBm on pin VS2 433.92 MHz/10dBm 868.3 MHz/5dBm 868.3 MHz/10dBm Supply current TX 12.12 mode *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA5823/ATA5824 88 = –40°C to +105°C, V amb VS2 Figure 4-1 on page 7. f has to be added. VSINT Pin ...
Page 89
... VS2 = 22 k 17, R_PWR dBm out = 5V VS2 = 22 k 17, R_PWR dBm out = 5V VS2 = 22 k 17, R_PWR 27 17, 27 ATA5823/ATA5824 = 4.4V to 5.6V 4.4V to 5.25V. Typical values at VSINT = 315.0 MHz/433.92 MHz/868.3 MHz unless otherwise RF Min. Typ. Max. I 12.7 16.9 FD4_VS2 I 13.8 18.4 FD5_VS2 I 15.6 20.8 FD6_VS2 ...
Page 90
... Time for Bit-check see 55) Bit-check time for a valid input signal f N Bit-check N Bit-check N Bit-check N Bit-check *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA5823/ATA5824 90 = –40°C to +105° amb VS1 = V VS1 VS2 Pin Symbol T T XDCLK T T ...
Page 91
... DATA_min T 33 CS_setup 32 Out_enable = Out_delay 31 Out_disable 35 T CS_disable 33 SCK_setup1 ATA5823/ATA5824 = 2.15V to 3.6V (battery application), and VS2 VSINT = and T = 25°C unless otherwise specified. VSINT amb Min. Typ. Max. 1.0 2.5 2.0 5.0 4.0 10.0 8.0 20 XDCLK 200 ...
Page 92
... PWR_ON high to positive edge on pin From every mode 18.2 IRQ (Figure 12-4 on except OFF mode page 46) *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA5823/ATA5824 92 = –40°C to +105°C. V amb VS1 = V VS1 VS2 Pin Symbol 33 SCK_setup2 33 SCK_hold Figure 3-1 ...
Page 93
... 29 N_PWR_ON_IRQ = 2.2 µ 29 Debounce T Startup_PLL_fd T Startup_Sig_Proc_fd T ATA5823/ATA5824 = 2.15V to 3.6V (battery application), and VS2 VSINT = and T = 25°C unless otherwise specified. VSINT amb Min. Typ. Max. 0.3 0.8 0.45 1.3 8195 8195 T T DCLK 798.5 798 ...
Page 94
... SCK_PHA input - low level input voltage 20.10 - high level input voltage *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA5823/ATA5824 94 = –40°C to +105° 2.15V to 3.6V (battery application) and V amb VS1 VS2 ...
Page 95
... V = 2.15V to 5.25V 250 µ 1000 µA = 2.15V to 5.25V –1500 µ µ –1500 µ ATA5823/ATA5824 = 2.15V to 3.6V (battery application) and V = 25°C unless otherwise specified. amb Min. Typ. Max. 0.25 Il 1.7 AVCC Ih 0.25 Il 1.7 AVCC Ih 0.15 0 – V – ...
Page 96
... Ordering Information Extended Type Number ATA5823-PLQW ATA5824-PLQW 23. Package Information Package: QFN Exposed pad 5.1 x 5.1 Dimensions in mm Not indicated tolerances ± 0. Drawing-No.: 6.543-5089.02-4 Issue: 1; 14.01.03 24. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document ...
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... Operation Modes .................................................................................... 52 15 Absolute Maximum Ratings .................................................................. 71 16 Thermal Resistance ............................................................................... 71 17 Electrical Characteristics: General ...................................................... 72 18 Electrical Characteristic: Battery Application ..................................... 86 19 Electrical Characteristics: Car Application ......................................... 88 20 Digital Timing Characteristics .............................................................. 90 21 Digital Port Characteristics ................................................................... 94 22 Ordering Information ............................................................................. 96 23 Package Information ............................................................................. 96 4829D–RKE–06/06 ATA5823/ATA5824 97 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...