LFXP3C-3TN100C LATTICE SEMICONDUCTOR, LFXP3C-3TN100C Datasheet - Page 93

• Manufacturer Part Number: LFXP3C-3TN100C
• Description: FPGA LatticeXP Family 3000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 100-Pin TQFP Tray
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFXP3C-3TN100C

• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296

Lattice Semiconductor
LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA
Number
Ball
G4
D2
D1
H4
H3
G3
G2
G1
H2
H1
M1
M2
N1
M3
M4
N2
R1
N3
N4
R2
F4
E2
E3
F3
F2
F1
E1
K4
K2
K3
K1
L2
L3
L4
L1
P1
P2
T1
J4
J2
J1
J3
-
-
-
-
-
-
-
PROGRAMN
Function
GNDIO7
GNDIO7
GNDIO7
GNDIO7
GNDIO7
GNDIO6
GNDIO6
VCCP0
GNDP0
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
PL15B
PL16A
PL16B
PL17A
PL17B
PL18A
PL18B
PL19A
PL19B
PL20A
PL20B
PL21A
PL21B
PL22A
PL23B
PL24A
PL24B
CCLK
PL2A
PL2B
PL3A
PL3B
PL4A
PL4B
PL5A
PL6B
PL7A
PL7B
PL8A
PL8B
PL9A
PL9B
Ball
Bank Diff.
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
-
-
LFXP10
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
LUM0_PLLC_FB_A
LUM0_PLLT_FB_A
LUM0_PLLC_IN_A
LUM0_PLLT_IN_A
Dual Function
PCLKT6_0
PCLKC6_0
VREF1_7
VREF2_7
VREF1_6
DQS
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PROGRAMN
Function
GNDIO7
GNDIO7
GNDIO7
GNDIO7
GNDIO7
GNDIO6
GNDIO6
VCCP0
GNDP0
PL10B
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL18A
PL19B
PL20A
PL20B
PL21A
PL21B
PL22A
PL22B
PL23A
PL23B
PL24A
PL24B
PL25A
PL25B
PL26A
PL27B
PL28A
PL28B
CCLK
PL6A
PL6B
PL7A
PL7B
PL8A
PL8B
PL9A
Ball
Bank Diff.
4-34
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
-
-
LFXP15
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
C
T
C
T
C
T
C
T
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
LUM0_PLLC_FB_A
LUM0_PLLT_FB_A
LUM0_PLLC_IN_A
LUM0_PLLT_IN_A
Dual Function
PCLKC6_0
PCLKT6_0
VREF1_7
VREF2_7
VREF1_6
DQS
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LatticeXP Family Data Sheet
PROGRAMN
Function
GNDIO7
GNDIO7
GNDIO7
GNDIO7
GNDIO7
GNDIO6
GNDIO6
GNDP0
VCCP0
PL10B
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL18A
PL19B
PL20A
PL20B
PL21A
PL21B
PL22A
PL22B
PL27A
PL27B
PL28A
PL28B
PL29A
PL29B
PL30A
PL31B
PL32A
PL32B
CCLK
PL6A
PL6B
PL7A
PL7B
PL8A
PL8B
PL9A
Ball
Bank Diff.
Pinout Information
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
-
-
LFXP20
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
C
C
C
C
C
T
T
T
T
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
LUM0_PLLC_FB_A
LUM0_PLLT_FB_A
LUM0_PLLC_IN_A
LUM0_PLLT_IN_A
Dual Function
PCLKC6_0
PCLKT6_0
VREF1_7
VREF2_7
VREF1_6
DQS
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-