FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA

XC5VLX50T-1FFG665I

Manufacturer Part NumberXC5VLX50T-1FFG665I
DescriptionFPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 LXT
XC5VLX50T-1FFG665I datasheets
Product Change Notification
 


Specifications of XC5VLX50T-1FFG665I

Package665FCBGAFamily NameVirtex®-5
Device Logic Units46080Typical Operating Supply Voltage1 V
Maximum Number Of User I/os360Ram Bits2211840
Number Of Logic Elements/cells46080Number Of Labs/clbs3600
Total Ram Bits2211840Number Of I /o360
Voltage - Supply0.95 V ~ 1.05 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case665-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithHW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates-  
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DS202 (v5.3) May 5, 2010
Virtex-5 FPGA Electrical Characteristics
Virtex®-5 FPGAs are available in -3, -2, -1 speed grades,
with -3 having the highest performance. Virtex-5 FPGA DC
and AC characteristics are specified for both commercial
and industrial grades. Except the operating temperature
range or unless otherwise noted, all the DC and AC
electrical parameters are the same for a particular speed
grade (that is, the timing characteristics of a -1 speed grade
industrial device are the same as for a -1 speed grade
commercial device). However, only selected speed grades
and/or devices might be available in the industrial range.
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The
parameters included are common to popular designs and
typical applications.
This Virtex-5 FPGA data sheet, part of an overall set of
documentation on the Virtex-5 family of FPGAs, is available
on the Xilinx website:
Virtex-5 FPGA DC Characteristics
Table 1: Absolute Maximum Ratings
Symbol
V
Internal supply voltage relative to GND
CCINT
V
Auxiliary supply voltage relative to GND
CCAUX
V
Output drivers supply voltage relative to GND
CCO
V
Key memory battery backup supply
BATT
V
Input reference voltage
REF
3.3V I/O input voltage relative to GND
(3)
V
3.3V I/O input voltage relative to GND (restricted to maximum of 100 user I/Os)
IN
2.5V or below I/O input voltage relative to GND (user and dedicated I/Os)
Current applied to an I/O pin, powered or unpowered
I
IN
Total current applied to all I/O pins, powered or unpowered
Voltage applied to 3-state 3.3V output
V
TS
Voltage applied to 3-state 2.5V or below output (user and dedicated I/Os)
T
Storage temperature (ambient)
STG
Maximum soldering temperature
T
SOL
T
Maximum junction temperature
J
Notes:
1.
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute
Maximum Ratings conditions for extended periods of time might affect device reliability.
2.
For soldering guidelines, refer to UG112: Device Package User Guide. For thermal considerations, refer to UG195: Virtex-5 FPGA Packaging and
Pinout Specification on the Xilinx website.
3.
3.3V I/O absolute maximum limit applied to DC and AC signals.
4.
For 3.3V I/O operation, refer to UG190: Virtex-5 FPGA User Guide, Chapter 6, 3.3V I/O Design Guidelines.
5.
For more flexibility in specific designs, a maximum of 100 user I/Os can be stressed beyond the normal specification for no more than 20% of a data period.
© 2006–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. PowerPC is a trademark of IBM Corp. and is used under license. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property
of their respective owners.
DS202 (v5.3) May 5, 2010
Product Specification
0
DC and Switching Characteristics
0
0
Virtex-5 Family Overview
Virtex-5 FPGA User Guide
Virtex-5 FPGA Configuration Guide
Virtex-5 FPGA XtremeDSP™ Design Considerations
Virtex-5 FPGA Packaging and Pinout Specification
Embedded Processor Block in Virtex-5 FPGAs Reference
Guide
Virtex-5 FPGA RocketIO™ GTP Transceiver User Guide
Virtex-5 FPGA RocketIO GTX Transceiver User Guide
Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User
Guide
Virtex-5 FPGA Integrated Endpoint Block User Guide for
PCI Express® Designs
Virtex-5 FPGA System Monitor User Guide
Virtex-5 FPGA PCB Designer’s Guide
All specifications are subject to change without notice.
Description
(4)
(user and dedicated I/Os)
(4)
(user and dedicated I/Os)
(2)
(2)
www.xilinx.com
Virtex-5 FPGA Data Sheet:
Product Specification
–0.5 to 1.1
–0.5 to 3.0
–0.5 to 3.75
–0.5 to 4.05
–0.5 to 3.75
–0.75 to 4.05
–0.95 to 4.4
(Commercial Temperature)
(5)
–0.85 to 4.3
(Industrial Temperature)
+ 0.5
–0.75 to V
CCO
±100
±100
–0.75 to 4.05
+ 0.5
–0.75 to V
CCO
–65 to 150
+
220
+
125
Units
V
V
V
V
V
V
V
V
mA
mA
V
V
°C
°C
°C
1

XC5VLX50T-1FFG665I Summary of contents

  • Page 1

    DS202 (v5.3) May 5, 2010 Virtex-5 FPGA Electrical Characteristics Virtex®-5 FPGAs are available in -3, -2, -1 speed grades, with -3 having the highest performance. Virtex-5 FPGA DC and AC characteristics are specified for both commercial and industrial grades. Except ...

  • Page 2

    Table 2: Recommended Operating Conditions Symbol Description Internal supply voltage relative to GND CCINT Internal supply voltage relative to GND, T Auxiliary supply voltage relative to GND, T (1) V CCAUX Auxiliary supply voltage relative to GND, T ...

  • Page 3

    ... Table 4. Speed and Temperature Grade Device -3 (C) XC5VLX20T N/A XC5VLX30 480 XC5VLX30T 507 XC5VLX50 651 XC5VLX50T 689 XC5VLX85 1072 XC5VLX85T 1115 XC5VLX110 1391 XC5VLX110T 1448 XC5VLX155 2615 XC5VLX155T 2674 XC5VLX220 ...

  • Page 4

    ... CCOQ CCO DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Speed and Temperature Grade Device -3 (C) XC5VLX20T N/A XC5VLX30 1.5 XC5VLX30T 1.5 XC5VLX50 2 XC5VLX50T 2 XC5VLX85 3 XC5VLX85T 3 XC5VLX110 4 XC5VLX110T 4 XC5VLX155 8 XC5VLX155T 8 XC5VLX220 N/A XC5VLX220T N/A ...

  • Page 5

    ... If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools. DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Speed and Temperature Grade Device -3 (C) N/A XC5VLX30 38 XC5VLX30T 43 XC5VLX50 57 XC5VLX50T 62 XC5VLX85 93 XC5VLX85T 98 XC5VLX110 125 XC5VLX110T 130 XC5VLX155 172 XC5VLX155T 177 XC5VLX220 ...

  • Page 6

    ... CCAUXMIN Device (1) Typ Typ XC5VLX20T 172 54 XC5VLX30 235 76 XC5VLX30T 246 86 XC5VLX50 320 114 XC5VLX50T 336 124 XC5VLX85 492 186 XC5VLX85T 515 196 Table 6: Power Supply Ramp Time Symbol V Internal supply voltage relative to GND CCINT V Output drivers supply voltage relative to GND CCO ...

  • Page 7

    SelectIO™ DC Input and Output Levels Values for V and V are recommended input voltages. Values for operating conditions at the V and V OL all standards meet their specifications. The selected standards are tested at a ...

  • Page 8

    HT DC Specifications (HT_25) Table Specifications Symbol DC Parameter V Supply Voltage CCO V Differential Output Voltage OD Δ V Change in V Magnitude Output Common Mode Voltage OCM Δ V Change in V ...

  • Page 9

    LVPECL DC Specifications (LVPECL_25) These values are valid when driving a 100Ω differential load only, i.e., a 100Ω resistor between the two receiver pins. The V levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant ...

  • Page 10

    Table 13: Processor Block MIB Switching Characteristics Clock Name Description Clock-to-out and setup relative to clock T CK_CONTROL T CK_ADDRESS T CK_DATA T CONTROL_CK T DATA_CK Table 14: Processor Block PLBM Switching Characteristics Clock Name Description Clock-to-out and setup relative ...

  • Page 11

    Table 17: Processor Block DMA0 Switching Characteristics Clock Name Description Clock-to-out and setup relative to clock T CK_CONTROL T CK_DATA T CONTROL_CK T DATA_CK Table 18: Processor Block DMA1 Switching Characteristics Clock Name Description Clock-to-out and setup relative to clock ...

  • Page 12

    Table 21: Processor Block DCR Switching Characteristics Clock Name Description Clock-to-out and setup relative to clock T CK_CONTROL T CK_ADDRESS T CK_DATA T CONTROL_CK T ADDRESS_CK T DATA_CK Table 22: Processor Block FCM Switching Characteristics Clock Name Description Clock-to-out and ...

  • Page 13

    GTP_DUAL Tile Specifications GTP_DUAL Tile DC Characteristics Table 24: Absolute Maximum Ratings for GTP_DUAL Tiles Symbol MGTAVCCPLL Analog supply voltage for the GTP_DUAL shared PLL relative to GND MGTAVTTTX Analog supply voltage for the GTP_DUAL transmitters relative to GND MGTAVTTRX ...

  • Page 14

    Table 27: GTP_DUAL Tile Quiescent Supply Current Symbol I Quiescent MGTAVTTTX (transmitter termination) supply current AVTTTXQ I Quiescent MGTAVCCPLL (PLL) supply current AVCCPLLQ I Quiescent MGTAVTTRX (receiver termination) supply current. Includes AVTTRXQ MGTAVTTRXCQ. I Quiescent MGTAVCC (analog) supply current AVCCQ ...

  • Page 15

    X-Ref Target - Figure P–N –V Figure 2: Peak-to-Peak Differential Output Voltage Table 29 summarizes the DC specifications of the clock input of the GTP_DUAL tile. voltage swing. Figure 4 shows the peak-to-peak differential clock input voltage ...

  • Page 16

    GTP_DUAL Tile Switching Characteristics Consult UG196:Virtex-5 FPGA RocketIO GTP Transceiver User Guide for further information. Table 30: GTP_DUAL Tile Performance Symbol F Maximum GTP transceiver data rate GTPMAX F Maximum PLL frequency GPLLMAX F Minimum PLL frequency GPLLMIN Table 31: ...

  • Page 17

    Table 33: GTP_DUAL Tile User Clock Switching Characteristics Symbol Description F TXOUTCLK maximum frequency TXOUT F RXRECCLK maximum frequency RXREC T RXUSRCLK maximum frequency RX T RXUSRCLK2 maximum frequency RX2 T TXUSRCLK maximum frequency TX T TXUSRCLK2 maximum frequency TX2 ...

  • Page 18

    Table 35: GTP_DUAL Tile Receiver Switching Characteristics Symbol F Serial data rate GTPRX OOB detect threshold R XOOBVDPP peak-to-peak Receiver spread-spectrum R XSST (1) tracking R Run length (CID) XRL Data/REFCLK PPM offset R XPPMTOL (2) tolerance (4) SJ Jitter ...

  • Page 19

    GTX_DUAL Tile Specifications GTX_DUAL Tile DC Characteristics Table 36: Absolute Maximum Ratings for GTX_DUAL Tiles Symbol MGTAVCCPLL Analog supply voltage for the GTX_DUAL shared PLL relative to GND MGTAVTTTX Analog supply voltage for the GTX_DUAL transmitters relative to GND MGTAVTTRX ...

  • Page 20

    Table 39: GTX_DUAL Tile Quiescent Supply Current Symbol I Quiescent MGTAVTTTX (transmitter termination) supply current AVTTTXQ I Quiescent MGTAVCCPLL (PLL) supply current AVCCPLLQ I Quiescent MGTAVTTRX (receiver termination) supply current. Includes AVTTRXQ MGTAVTTRXCQ. I Quiescent MGTAVCC (analog) supply current AVCCQ ...

  • Page 21

    X-Ref Target - Figure P–N –V Figure 7: Peak-to-Peak Differential Output Voltage Table 41 summarizes the DC specifications of the clock input of the GTX_DUAL tile. voltage swing. Figure 9 shows the peak-to-peak differential clock input voltage ...

  • Page 22

    GTX_DUAL Tile Switching Characteristics Consult UG198:Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further information. Table 42: GTX_DUAL Tile Performance Symbol F Maximum GTX transceiver data rate GTXMAX F Maximum PLL frequency GPLLMAX F Minimum PLL frequency GPLLMIN Table 43: ...

  • Page 23

    Table 45: GTX_DUAL Tile User Clock Switching Characteristics Symbol Description F TXOUTCLK maximum frequency TXOUT F RXRECCLK maximum frequency RXREC T RXUSRCLK maximum frequency RX T RXUSRCLK2 maximum frequency RX2 T TXUSRCLK maximum frequency TX T TXUSRCLK2 maximum frequency TX2 ...

  • Page 24

    Table 46: GTX_DUAL Tile Transmitter Switching Characteristics (Cont’d) Symbol (2) T Total Jitter J3.75 D Deterministic Jitter J3.75 (2) T Total Jitter J3.2 D Deterministic Jitter J3.2 (2) T Total Jitter J3.2L D Deterministic Jitter J3.2L (2) T Total Jitter ...

  • Page 25

    Table 47: GTX_DUAL Tile Receiver Switching Characteristics (Cont’d) Symbol JT_SJ Sinusoidal Jitter 750 JT_SJ Sinusoidal Jitter 150 SJ Jitter Tolerance with Stressed Eye Total Jitter with Stressed JT_TJSE 4.25 (7) Eye Sinusoidal Jitter with JT_SJSE 4.25 Stressed Eye Notes: 1. ...

  • Page 26

    System Monitor Analog-to-Digital Converter Specification Table 51: Analog-to-Digital Specifications Parameter Symbol AV = 2.5V ± 2 2.5V REFP REFN DC Accuracy: All external input channels such as V and Common Mode = 0V Resolution Integral Nonlinearity ...

  • Page 27

    Table 51: Analog-to-Digital Specifications (Cont’d) Parameter Symbol (4) External Reference Inputs Positive Reference Input V REFP Voltage Range Negative Reference Input V REFN Voltage Range Input current I REF Power Requirements Analog Power Supply AV DD Analog Supply Current AI ...

  • Page 28

    Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Virtex-5 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as ...

  • Page 29

    ... DSP48E 48-bit Counter DSP48E 48-bit Comparator DSP48E bit Pipelined Multiplier DSP48E Direct 4-tap FIR Filter Pipelined DSP48E Systolic n-tap FIR Filter Pipelined Notes: 1. Device used is the XC5VLX50T- FF1136 Table 53: Interface Performances Description Networking Applications (1) SFI-4.1 (SDR LVDS Interface) (2) SPI-4.2 (DDR LVDS Interface) ...

  • Page 30

    ... Listed below are representative values. DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Table 54: Virtex-5 Device Speed Grade Designations Speed Grade Designations Device Advance XC5VLX20T XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T ...

  • Page 31

    ... DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Table 55: Virtex-5 Device Production Software and Speed Specification Release Speed Grade Designations Device XC5VLX20T XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T ...

  • Page 32

    IOB Pad Input/Output/3-State Switching Characteristics Table 56 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays described as the delay from IOB pad through the IOPI input ...

  • Page 33

    Table 56: IOB Switching Characteristics (Cont’d) I/O Standard LVTTL, Fast LVTTL, Fast LVTTL, Fast LVTTL, Fast LVTTL, Fast LVTTL, Fast LVTTL, Fast LVCMOS33, Slow ...

  • Page 34

    Table 56: IOB Switching Characteristics (Cont’d) I/O Standard LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Fast LVCMOS18, Fast ...

  • Page 35

    Table 56: IOB Switching Characteristics (Cont’d) I/O Standard LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2_15 GTL_DCI GTLP_DCI LVPECL_25 HSTL_I_12 HSTL_I_DCI HSTL_II_DCI HSTL_II_T_DCI HSTL_III_DCI HSTL_IV_DCI HSTL_I_DCI_18 HSTL_II_DCI_18 HSTL_II _T_DCI_18 HSTL_III_DCI_18 HSTL_IV_DCI_18 DIFF_HSTL_I_18 DIFF_HSTL_I_DCI_18 DIFF_HSTL_I DIFF_HSTL_I_DCI DIFF_HSTL_II_18 DIFF_HSTL_II_DCI_18 DIFF_HSTL_II DIFF_HSTL_II_DCI SSTL2_I_DCI SSTL2_II_DCI SSTL2_II_T_DCI SSTL18_I SSTL18_II SSTL18_I_DCI ...

  • Page 36

    Table 56: IOB Switching Characteristics (Cont’d) I/O Standard DIFF_SSTL2_I DIFF_SSTL2_I_DCI DIFF_SSTL18_I DIFF_SSTL18_I_DCI DIFF_SSTL2_II DIFF_SSTL2_II_DCI DIFF_SSTL18_II DIFF_SSTL18_II_DCI Table 57: IOB 3-state ON Output Switching Characteristics (T Symbol T T input to Pad high-impedance IOTPHZ DS202 (v5.3) May 5, 2010 Product Specification ...

  • Page 37

    I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 58 shows the test setup parameters used for measuring input delay. Table 58: Input Delay Measurement Methodology Description LVTTL (Low-Voltage Transistor-Transistor Logic) LVTTL LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS, 2.5V LVCMOS, 1.8V ...

  • Page 38

    Output Delay Measurements Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4” of FR4 microstrip trace. Standard termination was used for all testing. The propagation delay of the 4” trace is characterized separately ...

  • Page 39

    Table 59: Output Delay Measurement Methodology (Cont’d) Description HSTL, Class IV HSTL, Class I, 1.8V HSTL, Class II, 1.8V HSTL, Class III, 1.8V HSTL, Class IV, 1.8V SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL, Class II, 1.8V SSTL, ...

  • Page 40

    Input/Output Logic Switching Characteristics Table 60: ILOGIC Switching Characteristics Symbol Setup/Hold T /T CE1 pin Setup/Hold with respect to CLK ICE1CK ICKCE1 T /T SR/REV pin Setup/Hold with respect to CLK ISRCK ICKSR pin Setup/Hold with respect ...

  • Page 41

    Table 61: OLOGIC Switching Characteristics Symbol Setup/Hold T /T D1/D2 pins Setup/Hold with respect to CLK ODCK OCKD T /T OCE pin Setup/Hold with respect to CLK OOCECK OCKOCE T /T SR/REV pin Setup/Hold with respect to CLK OSRCK OCKSR ...

  • Page 42

    Input Serializer/Deserializer Switching Characteristics Table 62: ISERDES Switching Characteristics Symbol Setup/Hold for Control Lines BITSLIP pin Setup/Hold with respect to CLKDIV ISCCK_BITSLIP ISCKC_BITSLIP ( pin Setup/Hold with respect to CLK (for CE1) ISCCK_CE ...

  • Page 43

    Output Serializer/Deserializer Switching Characteristics Table 63: OSERDES Switching Characteristics Symbol Setup/Hold input Setup/Hold with respect to CLKDIV OSDCK_D OSCKD_D ( input Setup/Hold with respect to CLK OSDCK_T OSCKD_T ( input Setup/Hold ...

  • Page 44

    Input/Output Delay Switching Characteristics Table 64: Input/Output Delay Switching Characteristics Symbol IDELAYCTRL T Reset to Ready for IDELAYCTRL IDELAYCTRLCO_RDY F REFCLK frequency IDELAYCTRL_REF IDELAYCTRL_REF_PRECISION REFCLK precision T Minimum Reset pulse width IDELAYCTRL_RPW IODELAY T IODELAY Chain Delay Resolution IDELAYRESOLUTION Pattern ...

  • Page 45

    Table 65: CLB Switching Characteristics (Cont’d) Symbol T CX inputs to CMUX output CXB T CX inputs to DMUX output CXD T DX inputs to DMUX output DXD T An input to COUT output OPCYA T Bn input to COUT ...

  • Page 46

    CLB Distributed RAM Switching Characteristics (SLICEM Only) Table 66: CLB Distributed RAM Switching Characteristics Symbol Sequential Delays T Clock to A – B outputs SHCKO T Clock to AMUX – BMUX outputs SHCKO_1 Setup and Hold Times Before/After Clock CLK ...

  • Page 47

    Block RAM and FIFO Switching Characteristics Table 68: Block RAM and FIFO Switching Characteristics Symbol Block RAM and FIFO Clock to Out Delays (1) T and T Clock CLK to DOUT output (without output RCKO_DO RCKO_DOR register) Clock CLK to ...

  • Page 48

    Table 68: Block RAM and FIFO Switching Characteristics (Cont’d) Symbol Reset Delays T Reset RST to FIFO Flags/Pointers RCO_FLAGS Maximum Frequency F Block RAM in all modes MAX F Block RAM in cascade configuration MAX_CASCADE F FIFO in all modes ...

  • Page 49

    Table 69: DSP48E Switching Characteristics (Cont’d) Symbol TDSPCCK_CEMM/TDSPCKC_CEMM TDSPCCK_CEPP/TDSPCKC_CEPP Setup and Hold Times of the RST Pins TDSPCCK_{RSTAA, RSTBB}/ TDSPCKC_{RSTAA, RSTBB} TDSPCCK_RSTCC/ TDSPCKC_RSTCC TDSPCCK_RSTMM/ TDSPCKC_RSTMM TDSPCCK_RSTPP/TDSPCKC_RSTPP Combinatorial Delays from Input Pins to Output Pins TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_M TDSPDO_{AP, ACRYOUT, ...

  • Page 50

    Table 69: DSP48E Switching Characteristics (Cont’d) Symbol TDSPDO_{PCINPCOUT, CRYCINPCOUT, MULTSIGNINPCOUT, PCINCRYCOUT, CRYCINCRYCOUT, MULTSIGNINCRYCOUT, PCINMULTSIGNOUT, CRYCINMULTSIGNOUT, MULTSIGNINMULTSIGNOUT} Clock to Outs from Output Register Clock to Output Pins TDSPCKO_{PP, CRYOUTP} TDSPCKO_{CRYCOUTP, PCOUTP, MULTSIGNOUTP} Clock to Outs from Pipeline Register Clock to Output ...

  • Page 51

    Configuration Switching Characteristics Table 70: Configuration Switching Characteristics Symbol Power-up Timing Characteristics POR T ICCK T PROGRAM Master/Slave Serial Mode Programming Switching T /T DCCK CCKD T /T DSCCK SCCKD T CCO F MCCK F MCCKTOL F ...

  • Page 52

    Table 70: Configuration Switching Characteristics (Cont’d) Symbol BPI Master Flash Mode Programming Switching (4) T BPICCO T /T BPIDCC BPICCD T INITADDR SPI Master Flash Mode Programming Switching T /T SPIDCC SPIDCCD T SPICCM T SPICCFC T /T FSINIT FSINITH ...

  • Page 53

    Clock Buffers and Networks Table 71: Global Clock Switching Characteristics (Including BUFGCTRL) Symbol ( pins Setup/Hold BCCCK_CE BCCKC_CE ( pins Setup/Hold BCCCK_S BCCKC_S BUFGCTRL delay from (2) T BCCKO_O I0/ Maximum Frequency ...

  • Page 54

    Table 73: Regional Clock Switching Characteristics (BUFR) Symbol Clock to out delay from T BRCKO_O Clock to out delay from with Divide Bypass BRCKO_O_BYP attribute set T Propagation delay from BRDO_CLRO CLR to ...

  • Page 55

    PLL Switching Characteristics Table 74: PLL Specification Symbol F Maximum Input Clock Frequency INMAX F Minimum Input Clock Frequency INMIN F Maximum Input Clock Period Jitter INJITTER F Allowable Input Duty Cycle: 19—49 MHz INDUTY Allowable Input Duty Cycle: 50—199 ...

  • Page 56

    Table 75: PLL in PMCD Mode Switching Characteristics Symbol T /T REL Setup and Hold for all Outputs PLLCCK_REL PLLCKC_REL T Maximum Clock Propagation Delay PLLCCKO CLKIN_FREQ_MAX Maximum Input Frequency CLKIN_FREQ_MIN Minimum Input Frequency CLKIN_DUTY_CYCLE Allowable Input Duty Cycle: 1—49 ...

  • Page 57

    DCM Switching Characteristics Table 76: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode Symbol Outputs Clocks (Low Frequency Mode) F 1XLFMSMIN F 1XLFMSMAX F 2XLFMSMIN F 2XLFMSMAX F DVLFMSMIN F DVLFMSMAX F FXLFMSMIN F FXLFMSMAX Input Clocks (Low ...

  • Page 58

    Table 77: Operating Frequency Ranges for DCM in Maximum Range (MR) Mode Symbol Outputs Clocks (Low Frequency Mode) F 1XMRMIN F 1XMRMAX F 2XMRMIN F 2XMRMAX F DLLMRMIN F DLLMRMAX F FXMRMIN F FXMRMAX Input Clocks (Low Frequency Mode) F ...

  • Page 59

    Table 78: Input Clock Tolerances Symbol Duty Cycle Input Tolerance ( DUTYCYCRANGE_1 T DUTYCYCRANGE_1_50 T DUTYCYCRANGE_50_100 T DUTYCYCRANGE_100_200 T DUTYCYCRANGE_200_400 T DUTYCYCRANGE_400 Input Clock Cycle-Cycle Jitter (Low Frequency Mode) T CYCLFDLL T CYCLFFX Input Clock Cycle-Cycle Jitter (High ...

  • Page 60

    Output Clock Jitter Table 79: Output Clock Jitter Symbol Clock Synthesis Period Jitter T PERJITT_0 T PERJITT_90 T PERJITT_180 T PERJITT_270 T PERJITT_2X T PERJITT_DV1 T PERJITT_DV2 T PERJITT_FX Notes: 1. Values for this parameter are available in the Architecture ...

  • Page 61

    Table 81: Miscellaneous Timing Parameters Symbol Time Required to Achieve LOCK T DLL output – Frequency range > 240 MHz DLL_240 T DLL output – Frequency range 120 - 240 MHz DLL_120_240 T DLL output – Frequency range 60 - ...

  • Page 62

    ... Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Description XC5VLX20T XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 ...

  • Page 63

    ... IOB and CLB flip-flops are clocked by the global clock net. 2. DCM output jitter is already included in the timing calculation. DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Description XC5VLX20T XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T ...

  • Page 64

    ... IOB and CLB flip-flops are clocked by the global clock net. 2. DCM output jitter is already included in the timing calculation. DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Description XC5VLX20T XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T ...

  • Page 65

    ... IOB and CLB flip-flops are clocked by the global clock net. 2. PLL output jitter is included in the timing calculation. DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Description XC5VLX20T XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T ...

  • Page 66

    ... IOB and CLB flip-flops are clocked by the global clock net. 2. PLL output jitter is included in the timing calculation. DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Description XC5VLX20T XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T ...

  • Page 67

    ... IOB and CLB flip-flops are clocked by the global clock net. 2. DCM and PLL output jitter are already included in the timing calculation. DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Description XC5VLX20T XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T ...

  • Page 68

    ... IOB and CLB flip-flops are clocked by the global clock net. 2. DCM and PLL output jitter are already included in the timing calculation. DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Description XC5VLX20T XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T ...

  • Page 69

    ... PHFD Global Clock and IFF DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Description Device XC5VLX20T (2) without DCM or PLL XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T XC5VSX240T www ...

  • Page 70

    Table 91: Global Clock Setup and Hold Without DCM or PLL (Cont’d) Symbol Full Delay (Legacy Delay or Default Delay) PSFD PHFD Global Clock and IFF Notes: 1. Setup and Hold times are measured over worst case ...

  • Page 71

    ... No Delay Global Clock and IFF PSDCM PHDCM System-Synchronous Mode DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Description Device (2) with DCM in XC5VLX20T XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T XC5VSX240T www ...

  • Page 72

    Table 92: Global Clock Setup and Hold With DCM in System-Synchronous Mode (Cont’d) Symbol Delay Global Clock and IFF PSDCM PHDCM System-Synchronous Mode Notes: 1. Setup and Hold times are measured over worst case conditions (process, ...

  • Page 73

    ... No Delay Global Clock and IFF PSDCM0 PHDCM0 Source-Synchronous Mode DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Description Device (2) with DCM in XC5VLX20T XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T XC5VSX240T www ...

  • Page 74

    Table 93: Global Clock Setup and Hold With DCM in Source-Synchronous Mode (Cont’d) Symbol Delay Global Clock and IFF PSDCM0 PHDCM0 Source-Synchronous Mode Notes: 1. Setup and Hold times are measured over worst case conditions (process, ...

  • Page 75

    ... No Delay Global Clock and IFF PSPLL PHPLL System-Synchronous Mode DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Description Device (2) with PLL in XC5VLX20T XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T XC5VSX240T www ...

  • Page 76

    Table 94: Global Clock Setup and Hold With PLL in System-Synchronous Mode (Cont’d) Symbol Delay Global Clock and IFF PSPLL PHPLL System-Synchronous Mode Notes: 1. Setup and Hold times are measured over worst case conditions (process, ...

  • Page 77

    ... No Delay Global Clock and IFF PSPLL0 PHPLL0 Source-Synchronous Mode DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Description Device (2) with PLL in XC5VLX20T XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T XC5VSX240T www ...

  • Page 78

    Table 95: Global Clock Setup and Hold With PLL in Source-Synchronous Mode (Cont’d) Symbol Delay Global Clock and IFF PSPLL0 PHPLL0 Source-Synchronous Mode Notes: 1. Setup and Hold times are measured over worst case conditions (process, ...

  • Page 79

    ... T DCM and PLL in System-Synchronous Mode PHDCMPLL DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Description Device (2) with XC5VLX20T XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T XC5VSX240T www ...

  • Page 80

    Table 96: Global Clock Setup and Hold With DCM and PLL in System-Synchronous Mode (Cont’d) Symbol Delay Global Clock and IFF PSDCMPLL T DCM and PLL in System-Synchronous Mode PHDCMPLL Notes: 1. Setup and Hold times are ...

  • Page 81

    ... PLL in Source-Synchronous Mode PHDCMPLL_0 DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Description Device 32. (2) with DCM and XC5VLX20T XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T XC5VSX50T XC5VSX95T XC5VSX240T www ...

  • Page 82

    Table 97: Global Clock Setup and Hold With DCM and PLL in Source-Synchronous Mode Symbol Delay Global Clock and IFF PSDCMPLL_0 T PLL in Source-Synchronous Mode PHDCMPLL_0 Notes: 1. Setup and Hold times are measured over worst ...

  • Page 83

    ... Timing Analyzer tools to evaluate clock skew specific to the application. DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Description Device (1) (2) XC5VLX20T XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T XC5VSX35T ...

  • Page 84

    ... Package trace length information is available for these device/package combinations. This information can be used to deskew the package. DS202 (v5.3) May 5, 2010 Product Specification Virtex-5 FPGA Data Sheet: DC and Switching Characteristics Description Device (1) XC5VLX20T XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T XC5VLX110 XC5VLX110T XC5VLX155 XC5VLX155T XC5VLX220 XC5VLX220T XC5VLX330 XC5VLX330T ...

  • Page 85

    Table 100: Sample Window Symbol T Sampling Error at Receiver Pins SAMP T Sampling Error at Receiver Pins using BUFIO SAMP_BUFIO Notes: 1. This parameter indicates the total sampling error of Virtex-5 FPGA DDR input registers across voltage, temperature, and ...

  • Page 86

    Date Version 09/06/06 2.0 • Added new sections for LXT devices and added LXT devices to the appropriate tables. The addition of the GTP_DUAL Tile Specifications • Changed maximum V • Updated values and added T • Revised the cascade ...

  • Page 87

    Date Version 02/02/07 3.0 • Added XC5VSX35T, XC5VSX50T, and SX5VSX95T devices to appropriate tables. • Revised the I • Revised the I • Added values to • Minor added notes and changed descriptions in • Revised the SFI-4.1 (SDR LVDS ...

  • Page 88

    Date Version 05/18/07 3.1 • Added typical values for n and r in • Revised and added values to • Revised standard I/O levels in • Additions and updates to and Table • Added • Changed the design software version ...

  • Page 89

    Date Version 06/26/07 3.3 • Added conditions to DV • Changed the F • Updated GTP maximum line rates to 3.75 Gb/s in • Updated maximum frequencies in • Added 3.75 Gb/s condition and changed maximum value of F • ...

  • Page 90

    Date Version 03/31/08 4.0 • Added XC5VFX30T, XC5VFX70T, XC5VFX100T, XC5VFX130T, XC5VFX200T devices to appropriate tables. • Updated • Added • Corrected MGTAVCC in • Updated MGTR • Changed the symbol names to F • Moved the • Added notes to ...

  • Page 91

    Date Version 12/02/08 4.8 • Added I • In Table 32, page • Changed Conditions for T • In Table 35, page • In Table 45, page • In Table 46, page • In Table 54, page • In Table ...