LAN9215-MT Standard Microsystems (SMSC), LAN9215-MT Datasheet - Page 84

• Manufacturer Part Number: LAN9215-MT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9215-MT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Revision 2.7 (03-15-10)
5.3.9
31-25
23-21
16-19
BITS
15-7
6-5
24
20
4
Reserved
AMDIX_EN Strap State. This read-only bit reflects the state of the
AMDIX_EN strap pin (pin 73). This pin can be overridden by PHY Registers
27.15 and 27.13
Reserved
Must Be One (MBO). This bit must be set to “1” for normal device
operation.
TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values
to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the
space allocated by TX_FIF_SIZ, and the TX data FIFO consumes the
remaining space specified by TX_FIF_SZ. The minimum size of the TX
FIFOs is 2KB (TX data and status combined). The TX data FIFO is used for
both TX data and TX commands.
The RX Status and data FIFOs consume the remaining space, which is
equal to 16KB – TX_FIF_SIZ. See
Configurable FIFO Memory Allocation," on page 86
Reserved
PHY Clock Select (PHY_CLK_SEL). This field is used to switch between
the internal and external MII clocks (RX_CLK and TX_CLK). This field is
encoded as follows:
Notes:
Serial Management Interface Select (SMI_SEL). This bit is used to switch
the SMI port (MDIO and MDC) between the internal PHY and the external
MII port. When this bit is cleared to ‘0’, the internal PHY is selected, and all
SMI transactions will be to the internal PHY. When this bit is set to ‘1’, the
external MII port is selected, and all SMI transactions will be to the external
PHY. This bit functions independent of EXT_PHY_EN. When this bit is set,
the internal MDIO and MDC signals are driven low. When this bit is cleared,
the external MIDIO signal is tri-stated, and the MDC signal is driven low.
Note:
This field does not control multiplexing of the SMI port or other MII signals.
There are restrictions on the use of this field. Please refer to
"MII Interface - External MII Switching," on page 46
HW_CFG—Hardware Configuration Register
Note: The transmitter and receiver must be stopped before writing to this register. Refer to
---------------------------------------------------
[6]
0
0
1
1
Offset:
This bit does not control the multiplexing of other MII signals.
[5]
3.12.8, "Stopping and Starting the Transmitter," on page 58
Starting the Receiver," on page 62
0
1
0
1
MII Clock Source
Internal PHY
External MII Port
Clocks Disabled
Internal PHY
DESCRIPTION
74h
Section 5.3.9.1, "Allowable settings for
DATASHEET
84
for details on stopping the transmitter and receiver.
for more information.
Size:
for details.
16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support
Section 3.11,
and
32 bits
Section 3.13.4, "Stopping and
TYPE
R/W
R/W
R/W
R/W
RO
RO
RO
RO
DEFAULT
SMSC LAN9215
AMDIX
Strap
00b
Datasheet
Pin
5h
0
0
-
-
-
Section