HI-8482DT Holt Integrated Circuits, HI-8482DT Datasheet
HI-8482DT
Specifications of HI-8482DT
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HI-8482DT Summary of contents
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... March 2007 GENERAL DESCRIPTION The HI-8482 bus interface unit is a silicon gate CMOS de- vice designed as a dual differential line receiver in accor- dance with the requirements of the ARINC 429 bus speci- fication. The device translates incoming ARINC 429 sig- nals to normal CMOS/TTL levels on each of its two inde- pendent receive channels ...
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... NOR function of OUTA and OUTB. The test inputs logically disconnect the outputs of the comparators from OUTA and OUTB and force the device outputs to one of the three valid states (Figure 5). This alleviates having to ground the ARINC inputs during test mode operation. ...
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... HI-8482 ground (GND) connection should be sturdy and isolated from large switching currents to provide a quiet ground reference. The HI-8482 can be used with HI-3182 or HI-8585 Line Drivers to provide a complete analog ARINC 429 interface solution. A simple application, which can be used in systems requiring a repeater type circuit for long transmissions or for test interfaces, is given in The Figure 3 ...
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... INPUT ARINC input terminal A of channel 2 TIMING DIAGRAMS +10V ARINC DIFFERENTIAL 0V INPUT -10V OUTA OUTB +5V TESTA 0V +5V TESTB 0V OUTA (test) OUTB (test) HI-8482 SYMBOL FUNCTION IN2B INPUT OUT1A OUTPUT OUT1B OUTPUT OUT2A OUTPUT OUT2B OUTPUT TESTA INPUT TESTB INPUT +V POWER L +Vs ...
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... Voltage - sourcing 2.8mA Voltage - sinking 100µA Voltage - sinking 2.0mA Rise time Fall time Propagation delay - low to high (ARINC) Propagation delay - high to low (ARINC) Propagation delay - low to high (TESTA/B) Propagation delay - low to high (TESTA/B) Supply current +VS current +VS current -VS current -VS current +VL current +VL current Notes: 1 ...
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... TESTA - IN1A CAP2B - CAP1B IN2B - IN1B OUT2B - OUT1A IN2A - GND CAP2A - N/C OUT2A - OUT1B + N HOLT INTEGRATED CIRCUITS 6 HI-8482S 18 - IN1A HI-8482ST 17 - CAP1B HI-8482SM- IN1B 15 - OUT1A 20-PIN 14 - GND CERAMIC LCC 20 - TESTB 19 - CAP1A 18 - IN1A 17 - CAP1B HI-8482D HI-8482DT 16 - IN1B 15 - OUT1A 20-PIN 14 - GND CERDIP OUT1B ...
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... RANGE -40°C TO +85°C I -55°C TO +125°C T -55°C TO +125°C M PACKAGE DESCRIPTION 20 PIN CERAMIC SIDE BRAZED DIP (20C) 20 PIN CERAMIC LEADLESS CHIP CARRIER (20S) TEMPERATURE FLOW RANGE -40°C TO +85°C I -55°C TO +125°C T PACKAGE DESCRIPTION 20 PIN CERDIP (20D) ...
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... BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-8482 PACKAGE DIMENSIONS .5035 ± .0075 (12.789 ± .191) .295 ± .002 (7.493 ± .051) .018 typ (.457) 0° to 8° ...
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... BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-8482 PACKAGE DIMENSIONS .070 max 1.060 max (1.778 max) (26.924 max) .288 ±.005 (7.315 ±.127) ...
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... CERAMIC LEADLESS CHIP CARRIER .040 x 45° (1.016 x 45°) .020 INDEX (.508) PIN 1 .350 ±.008 (8.890 ±.203) SQ. BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 20-PIN J-LEAD CERQUAD .375 ± .008 (9.525 ± ...