SI3056-D-FSR Silicon Laboratories Inc, SI3056-D-FSR Datasheet - Page 8

• Manufacturer Part Number: SI3056-D-FSR
• Description: Modem Chip Chipset 56Kbps 16-Pin SOIC T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3056-D-FSR

• Package: 16SOIC
• Main Category: Chipset
• Maximum Data Rate: 56 Kbps
• Typical Operating Supply Voltage: 3.3 V
• Power Supply Type: Analog
• Typical Supply Current: 15 mA
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V
• Lead Free Status / RoHS Status: Compliant

Table 4. AC Characteristics
(V
Si3018/19/10
8
Parameter
Sample Rate
PLL Output Clock Frequency
Transmit Frequency Response
Receive Frequency Response
Receive Frequency Response
Transmit Full Scale Level
Receive Full Scale Level
Dynamic Range
Dynamic Range
Dynamic Range
Transmit Total Harmonic
Distortion
Transmit Total Harmonic
Distortion
Notes:
D
1. See Figure 26 on page 37.
2. Measured at TIP and RING with 600 Ω termination at 1 kHz, as shown in Figure 1.
3. With FULL = 1, the transmit and receive full scale level of +3.2 dBm can be achieved with a 600 Ω ac termination, while
4. Receive full scale level produces –0.9 dBFS at SDO.
5. DR = 20 x log (RMS V
6. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths. V
7. When using the Si3010 line-side, the typical DR values will be approximately 10 dB lower.
8. THD = 20 x log (RMS distortion/RMS signal). V
9. When using the Si3010 line-side, the typical THD values will be approximately 10 dB higher.
10. DR
11. Available on the Si3019 line-side device only.
= 3.0 to 3.6 V, T
the transmit and receive level in dBm varies with reference impedance, the DAA will transmit and receive 1 dBV into all
reference impedances in “FULL” mode. With FULL2 = 1, the transmit and receive full scale level of +6.0 dBm can be
achieved with a 600 Ω ac termination. In “FULL2” mode, the DAA will transmit and receive +1.5 dBV into all reference
impedances.
harmonics. V
application circuit in Figure 17. With the enhanced CID circuit, the V
increases to 62 dB.
8,9
8,9
CID
1
= 20 x log (RMS V
5,6,7
5,6,7
5,6,7
A
FS
= 0 to 70 °C; see Figure 17 on page 18)
is the 0 dBm full-scale level.
2,4
2,3
FS
/RMS V
1
CID
/RMS V
IN
Symbol
).+ 20 x log (RMS V
F
THD
THD
V
V
DR
DR
DR
PLL1
IN
Fs
FS
FS
) + 20 x log(RMS V
ILIM = 0, DCV = 00, DCR = 0,
ILIM = 0, DCV = 00, DCR = 0,
ILIM = 0, DCV = 11, DCR = 0,
ILIM = 1, DCV = 11, DCR = 0,
ILIM = 0, DCV = 11, DCR = 0,
IN
I
I
F
L
I
L
Low –3 dBFS Corner,
Low –3 dBFS Corner,
I
I
FULL = 1
FULL = 1
Low –3 dBFS Corner
FULL2 = 1 (6.0 dBm)
FULL2 = 1 (6.0 dBm)
= 1 kHz, –3 dBFS, Fs = 10300 Hz.
L
L
L
PLL1
= 100 mA, MINI = 00
= 100 mA, MINI = 00
Rev. 1.05
FULL = 0 (0 dBm)
FULL = 0 (0 dBm)
= 50 mA, MINI = 00
= 20 mA, MINI = 11
= 20 mA, MINI = 11
Fs = F
Test Condition
IN
= (F
FILT = 1
/RMS noise). The RMS noise measurement excludes
FILT = 0
IN
/RMS noise). V
PLL2
11
11
MCLK
(3.2 dBm)
(3.2 dBm)
/5120
11
x
CID
M)/N
full-scale level is 1.5 V peak, and DR
CID
IN
is the 6 V full-scale level for the typical
= 1 kHz, –3 dBFS, Fs = 10300 Hz.
Min
7.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
98.304
1.58
2.16
1.58
2.16
Typ
200
–72
–78
1.1
1.1
—
80
80
80
0
5
Max
16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CID
V
V
V
V
V
V
MHz
Unit
kHz
PEAK
PEAK
PEAK
PEAK
PEAK
PEAK
Hz
Hz
Hz
dB
dB
dB
dB
dB