AM79C874VI AMD (ADVANCED MICRO DEVICES), AM79C874VI Datasheet
AM79C874VI
Specifications of AM79C874VI
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AM79C874VI Summary of contents
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... It includes on-chip input fil- tering and output waveshaping for unshielded twisted pair operation without requiring external filters or chokes. The NetPHY-1LP device can use 1:1 isolation transformers or 1.25:1 isolation transformers. 1.25:1 isolation transformers provide 20% lower transmit power consumption. A PECL interface is available for 100BASE-FX applications ...
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... BLOCK DIAGRAM MII Data Interface Interface MAC MDC/MDIO MII Serial Management Interface and Registers PHYAD[4: PCS PMA Framer Clock Recovery Carrier Detect Link Monitor Signal Detect Stream Cipher 4B/5B 25 MHz 10BASE-T 100BASE-X Control/Status 20 MHz PLL Clk Generator Test LED Control XTL+ XTL- ...
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... ISO 3 4 TGND1 REFCLK 5 CLK25 6 BURN_IN 7 RST 8 PWRDN 9 PLLVCC 10 PLLGND 11 OGND1 12 OVDD1 13 PHYAD[4]/10RXD- 14 PHYAD[3]/10RXD+ 15 PHYAD[2]/10TXD++ 16 PHYAD[1]/10TXD+ 17 PHYAD[0]/10TXD- 18 GPIO[0]/10TXD--/7Wire 19 GPIO[1]/TP125 22235K Am79C874 NetPHY-1LP Am79C874 60 EQVCC 59 ADPVCC 58 LEDDPX/LEDTXB 57 LEDSPD[1]/LEDTXA/CLK25EN 56 ANEGA 55 TECH_SEL[0] 54 TECH_SEL[1] 53 TECH_SEL[2] 52 CRVVCC ...
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... PACKAGE TYPE V = 80-Pin Thin Plastic Quad Flat Pack (PQT 80) SPEED OPTION Not Applicable DEVICE NUMBER/DESCRIPTION Am79C874 NetPHY-1LP Low Power 10/100-TX/FX Ethernet Transceiver VC Valid Combinations list configurations planned to be sup- VI ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and VD to check on newly released combinations ...
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... RELATED AMD PRODUCTS Part No. Description Integrated Controllers Am79C973B/ PCnet-FAST™ III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY Am79C975B Am79C976 PCnet-PRO™ 10/100 Mbps PCI Ethernet PCI Controller Am79C978A PCnet-Home™ Single-Chip 1/10 Mbps PCI Home Networking Controller Physical Layer Devices (Single-Port) Am79C901A HomePHY™ ...
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... Reverse Polarity Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Auto-Negotiation and Miscellaneous Functions .24 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Far-End Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 SQE (Heartbeat .25 Loopback Operation .25 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 LED Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Power Savings Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Selectable Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Power Down .29 Unplugged . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Idle Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PHY CONTROL AND MANAGEMENT BLOCK (PCM BLOCK . Am79C874 22235K ...
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... Register Administration for 100BASE-X PHY Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Description of the Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Bad Management Frame Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Serial Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Reserved Registers (Registers 8-15, 20, 22, 25-31 .36 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Commercial ( .42 Industrial ( .42 DC CHARACTERISTICS .42 SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 System Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 MLT-3 Signals ...
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... Figure 4. 10BASE-T Transmit /Receive Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Figure 5. Standard LED Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Figure 6. Advanced LED Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Figure 7. PHY Management Read and Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Figure 8. MLT-3 Receive Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Figure 9. MLT-3 and 10BASE-T Test Load with 1:1 Transformer Ratio . . . . . . . . . . . . . . . . . .45 Figure 10. MLT-3 and 10BASE-T Test Load with 1.25:1 Transformer Ratio . . . . . . . . . . . . . . .45 Figure 11 ...
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... Table 7. Standard LED Mode and Advanced LED Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table 8. Duplex LED Status Configuration in Advanced LED Mode1 . . . . . . . . . . . . . . . . . . . . . . .27 Table 9. Activity LED Configuration in Advanced LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 10. Clause 22 Management Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Table 11. PHY Address Setting Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Table 12. Supported Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Table 13. Serial Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Table 14. MII Management Control Register (Register .32 Table 15 ...
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... PWRDN 29 10 PLLVCC 30 11 PLLGND 31 12 OGND1 32 13 OVDD1 33 14 PHYAD[4]/10RXD PHYAD[3]/10RXD PHYAD[2]/10TXD PHYAD[1]/10TXD PHYAD[0]/10TXD- 38 GPIO[0]/10TXD--/ 19 39 7Wire 20 GPIO[1]/TP125 Pin Pin Name No. Pin Name MDIO 41 COL/10COL MDC 42 CRS/10CRS RXD[3] 43 INTR LEDSPD[0]/ RXD[2] 44 LEDBTA/FX_SEL ...
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... MII Register 16, bit 0 in which RX_CLK is held inactive (low) when no data is received. If RX_CLK is needed when LINK is not established, the NetPHY-1LP must be placed into digital loopback or force the link via reg- ister 21, bits 13 or 14. When 7-wire 10BASE-T mode is enabled, this pin will provide a 10 MHz clock ...
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... TXD[3:1] Transmit Data The MAC will source TXD[3:1] to the PHY. The data will be synchronous with TX_CLK when TX_EN is as- serted. The PHY will clock in the data based on the ris- ing edge of TX_CLK. TXD[0]/10TXD Transmit Data[0]/10 Mbps Transmit Data The MAC will source TXD[0] to the PHY. The data will be synchronous with TX_CLK when TX_EN is as- serted ...
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... Each pin should either be pulled low via a 1 kΩ − 4.7 kΩ resistor (set bit to zero) or left unconnected (set bit order to achieve the desired PHY ad- dress. New address changes take effect after a reset has been issued power up. ...
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MDC Management Data Clock This clock is sourced by the MAC and is used to synchronize MDIO data. When management is not used, this pin should be tied to ground. INTR Interrupt Output, High Impedance This pin is used to ...
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... ADPVCC, EQVCC, REFVCC, TVCC1, TVCC2 Power Pins These pins are 3.3 V power for sections of the NetPHY-1LP device as follows: PLLVCC is power for the PLL; OVDD1 and OVDD2 are power for the I/O; VDD1 and VDD2 are power for the digital logic; CRVVCC is power for clock recovery; AD- PVCC and EQVCC are power for the equalizer ...
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... MII Mode The purpose of the MII mode is to provide a simple, easy to implement connection between the MAC Rec- onciliation layer and the PHY. The MII is designed to make the differences between various media transpar- ent to the MAC sublayer. The MII consists of a nibble wide receive data bus, a ...
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... Pseudo-ECL (PECL) data stream to the fiber optic transmitter. See Figure 1. In the receive data path for 100 Mbps, the NetPHY-1LP transceiver receives an MLT-3 data stream from the network. For 100BASE-TX, it then recovers the clock ...
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... Both clocks are generated by an on-chip PLL clock synthesizer that is locked to an external 25-MHz clock source. In 100BASE-FX mode, the NetPHY-1LP device will by- pass the scrambler. The output data is an NRZI PECL signal. This PECL level signal will then drive the Fiber transmitter ...
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... The resulting sig- nal has fewer repetitive data patterns. After reset, the scrambler seed in each port will be set to the PHY address value to help improve the EMI per- formance of the device. The scrambled data stream is descrambled at the re- ceiver by adding it to the output of another random gen- erator. The receiver’ ...
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MII (TXD[3:0]) Name ...
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... Refer to Figure 3. 22235K Adaptive Equalizer The NetPHY-1LP device is designed to accommodate a maximum cable length of 140 meters UTP CAT-5 ca- ble. 140 meters of UTP CAT-5 cable has an attenuation 100 MHz. The typical attenuation of a 100 meter cable is 21 dB. The worst case attenuation is around 24-26 dB defined by TP-PMD ...
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... RX_CLK. PLL Clock Synthesizer The NetPHY-1LP device includes an on-chip PLL clock synthesizer that generates a 125 MHz and a 25 MHz clock for the 100BASE- 100 MHz and 20 MHz clock for the 10BASE-T and Auto-Negotiation opera- tions ...
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... Twisted Pair Interface Status The NetPHY-1LP transceiver will power up in the Link Fail state. The Auto-Negotiation algorithm will apply to allow it to enter the Link Pass state. A link-pulse detec- tion circuit constantly monitors the RX± ...
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... Auto-Negotiation and Miscellaneous Functions Auto-Negotiation The NetPHY-1LP device has the ability to negotiate its mode of operation over the twisted pair using the Auto- Negotiation mechanism defined in Clause 28 of the IEEE 802.3u specification. Auto-Negotiation may be enabled or disabled by hardware (ANEGA, pin 56) or software (MII Register 0, bit 12) control (see Table ). ...
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... MII Register 0 (speed and duplex bits) must be set by the MAC to achieve a link. 2. When Auto-Negotiation is enabled, these bits can be written but will be ignored by the PHY. 3. The advertised abilities in MII Register 4 cannot exceed the abilities of MII Register 1. Auto-Negotiation should always remain enabled. Hardware settings override software settings in registers. ...
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... Mbps and 100 Mbps after setting Register 0, bit 8 to force full duplex and bit 13 to set the speed. Reset The NetPHY-1LP device can be reset in the three fol- lowing ways: 1. During initial power on (with internal power on reset circuit). ...
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Mbps 10 Mbps Collision Duplex Transmit Receive Link (Note 1) Link (Note 2) Notes: 1. Use for non 7-wire interface configurations. 2. Use for 7-wire interface configurations. Table 8. Duplex LED Status Configuration in Advanced LED Mode Mode 10 ...
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... Therefore, the two modes of operation can be turned- on and turned-off independently. Whenever the Net- PHY-1LP device is set to operate in a 100BASE-TX mode, the 10BASE-T circuitry is powered down, and when in 10BASE-T mode, the 100BASE-TX circuitry is powered down. ...
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... Extra care in the layout to control capacitance on the board is required. Power Down Most of the NetPHY-1LP device can be disabled via the Power Down bit in MII Register 0, bit 11. Setting this bit will power down the entire device with the exception of the MDIO/MDC management circuitry ...
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... WRITE 1.1 01 The PHYAD field, which is five bits wide, allows 32 unique PHY addresses. The managed PHY layer de- vice that is connected to a station management entity via the MII interface has to respond to transactions addressed to the PHY address. A station management Table 11. PHY Address Setting Frame Structure ...
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... Disconnect Counter 24 Receive Error Counter 25-31 Reserved The Physical Address of the PHY is set using the pins defined as PHYAD[4:0]. These input signals are strapped externally and sampled as when reset goes high. The PHYAD pins can be reprogrammed via soft- ware. Serial Management Registers A detailed definition of each Serial Management regis- ter is provided in the following table ...
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... Power Down achieve the same result Normal operation Electrically isolate the PHY from MII. However, PHY is still able to respond to MDC/MDIO. The default value of this bit depends on ISODEF pin, i.e., ISODEF=1, ISO bit will set to 1, & ISODEF=0, ISO 0 10 Isolate bit will set to 0 ...
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... Able to perform Auto-Negotiation function; value is Auto-Negotiation determined by ANEGA pin Ability 0 = Unable to perform Auto-Negotiation function Link is established; however, if the NetPHY-1LP device link fails, this bit will be cleared and remain cleared until Register Link Status is read via management interface link is down Jabber condition detected. ...
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... Table 17. PHY Identifier 2 Register (Register 3) Reg Bit Name Description 3 15:10 OUI Assigned to the 19th through 24th bits of the OUI. 3 9:4 Model Number Six-bit manufacturer’s model number. 3 3:0 Revision Number Four-bit manufacturer’s revision number. Table 18. Auto-Negotiation Advertisement Register (Register 4) Reg ...
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Table 19. Auto-Negotiation Link Partner Ability Register in Base Page Format (Register 5) Reg Bit Name 5 15 Next Page 5 14 Acknowledge 5 13 Remote Fault 5 12:11 Reserved 5 10 Flow Control 5 9 100BASE-T4 100BASE-TX Full 5 ...
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... Previous value of transmitted link code word equals 10:0 CODE Message/Un-formatted Code Field. Reserved Registers (Registers 8-15, 20, 22, 25-31) The NetPHY-1LP device contains reserved registers at addresses 8-15, 20, 22, 25-31. These registers should be ignored when read and should not be written at any time Am79C874 ...
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Table 23. Miscellaneous Features Register (Register 16) Reg Bit Name Description 1= Repeater mode, full-duplex is inactive, and CRS only 16 15 Repeater responds to receive activity. SQE test function is also disabled. INTR will be active high if this ...
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Table 24. Interrupt Control/Status Register (Register 17) Reg Bit Name Description 17 15 Jabber_IE Jabber Interrupt Enable 17 14 Rx_Er_IE Receive Error Interrupt Enable 17 13 Page_Rx_IE Page Received Interrupt Enable 17 12 PD_Fault_IE Parallel Detection Fault Interrupt Enable 17 ...
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Table 26. Power/Loopback Register (Register 19) Reg Bit Name Description 19 15:7 Reserved Transmit transformer ratio selection 1.25 TP125 0 = 1:1 The default value of this bit is controlled by reset-read value of pin 20. ...
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... CONF_ALED 0 = Activity LED responds to receive and transmit operations for Half Duplex. LED responds to receive activity in Full Duplex operation. This bit should be ignored when Register 0.8 is set Select NetPHY-1LP device‘s Standard LED configuration LED_SEL 0 = Use the Advanced LED configuration Enable far-end-fault generation and detection function. ...
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Table 28. Disconnect Counter (Register 23) Reg Bit Name Description DLOCK drop 23 15:0 Count of PLL lock drop events (100 Mbps operation only) counter Table 29. Receive Error Counter Register (Register 24) Reg Bit Name Description 24 15:0 RX_ER ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . .-55°C to +150°C Ambient Temperature Under Bias . . . -55°C to +150°C Supply Voltage . . . . . . . . ...
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Table 30. DC Characteristics (continued) 10BASE-T Near-End Peak V 8 TX10NE Differential Voltage 9 I Output Leakage Current Input Capacitance XTL± Power Supply Current CC 1. Applies to TEST1/ FXR+, TEST0/FXR-, and SDI+ inputs only. ...
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SWITCHING WAVEFORMS Key to Switching Waveforms RX± WAVEFORM INPUTS OUTPUTS Must be Will be Steady Steady May Will be Change Changing from from May ...
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TX+ TX- Figure 9. MLT-3 and 10BASE-T Test Load with 1:1 Transformer Ratio 78.1 TX+ TX- Figure 10. MLT-3 and 10BASE-T Test Load with 1.25:1 Transformer Ratio V TXOS +V TXOUT TX± -V TXOUT Figure 11. Near-End 100BASE-TX Waveform ...
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V TX10NE TX 10BASE-T 0 Figure 12. 10BASE-T Waveform With 1:1 Transformer Ratio Pin 82.5 Ω Pin 130 Ω Figure 13. PECL Test Loads Am79C874 22236G-14 69 ...
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SWITCHING CHARACTERISTICS Note: Parametric values are the same for commercial devices and industrial devices. System Clock Signal Symbol Parameter Description t REFCLK Period CLK t REFCLK Width HIGH CLKH t REFCLK Width LOW CLKL t REFCLK Rise Time CLR t ...
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MII Management Signals Symbol Parameter Description t MDC Period MDPER t MDC Pulse Width HIGH MDWH t MDC Pulse Width LOW MDWL t MDIO Delay From Rising Edge of MDC MDPD t MDIO Setup Time to Rising Edge of MDC ...
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MII Signals Symbol Parameter Description t TX_ER,TX_EN, TXD[3:0] Setup Time to TX_CLK Rising Edge MTS100 t TX_ER, TX_EN, TXD[3:0] Hold time From TX_CLK Rising Edge MTH100 t Transmit Latency TX_EN Sampled by TX_CLK to First Bit of /J/ MTEJ100 t ...
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TX_CLK TX_EN CRS COL TX± Figure 19. 100 Mbps Transmit End of Packet Timing MTIDLE100 t MTDCRL100 t MTDCOL100 /T/ Am79C874 /J/ 22236G-21 22235K ...
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Symbol Parameter Description t CRS HIGH After First Bit of /J/ MRJCRH100 t COL HIGH After First Bit of /J/ MRJCOH100 t First Bit of /T/ to CRS LOW MRTCRL100 t First Bit of /T/ to COL LOW MRTCOL100 t ...
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Symbol Parameter Description t TX_EN, TXD10[3:0] Setup Time to TX_CLK Rising Edge MTS10 t TX_EN, TXD10[3:0] Hold time From TX_CLK Rising Edge MTH10 t Transmit Latency TX_EN Sampled by TX_CLK to Start of Packet MTEP10 t CRS Assert from TX_EN ...
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TX_CLK TX_EN CRS COL TX± Figure 23. 10 Mbps MII Transmit End of Packet Timing 22235K MTIDLE10 t MTDCRL10 t MTDCOL10 Am79C874 22236G-25 53 ...
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Symbol Parameter Description t CRS HIGH After Start of Packet MRPCRH10 t COL HIGH After Start of Packet MRPCOH10 RXD[3:0], RX_DV, RX_ER Valid after CRS HIGH tMRCHR10 t RXD[3:0], RX_DV, RX_ER Valid Prior to the Rising of RX_CLK10 MRRC10 t ...
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GPSI Signals Symbol Parameter Description t 10CRS HIGH To First Bit Of Data GCD t Rising Edge of 10RXCLK to 10RXD or 10CRS GRCD Bit Cell 1 RX ± 10CRS 10RXCLK 10RXD Figure 26. GPSI Receive Timing - Start of ...
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Symbol Parameter Description Delay from RX± going the Rising Edge of 10RXCLK, which t GDOFF clocks out the last bit of data on 10RXD t Rising Edge of 10RXCLK to 10RXD or 10CRS GRCD 0 Bit (N ...
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Table 42. 10 Mbps GPSI Transmit Timing Symbol Parameter Description Delay from the rising edge of the 10TXCLK which first clocks t GTTX 10TXEN HIGH to TX± toggling LOW 10TXCLK 10TXEN TX± Figure 30. GPSI Transmit Timing - Start of ...
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... PHYSICAL DIMENSIONS PQT80 (measured in millimeters) 80-Lead Thin Plastic Quad Flat Pack (PQT Am79C874 Dwg rev. AE; 8/99 PQT80 22235K ...
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... Revision [B.7] Errata Summary The NetPHY-1LP device has a total of 3 errata, all of which are minor and should not cause concern. All information below should be used in conjunction with the latest NetPHY-1LP Datasheet PID 22235, available on the AMD website (www ...
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... Minor edits G • Minor edits H • PHYAD pins: Specified using resistors in the range of 1 kΩ to 4.7 kΩ for setting PHYAD pins. In GPSI mode, PHYAD pins must be set to addresses other than 00h. • DC Characteristics added: V • DC Characteristics, added new values for: I LED component changes ...