KSZ8041NL Micrel Inc, KSZ8041NL Datasheet
KSZ8041NL
Specifications of KSZ8041NL
Available stocks
Related parts for KSZ8041NL
KSZ8041NL Summary of contents
Page 1
... The KSZ8041RNL is an enhanced RMII version of the KSZ8041NL that does not require a 50MHz system clock. It uses a 25MHz crystal for its input reference clock and outputs a 50MHz RMII reference clock to the MAC. ...
Page 2
... Pb-Free 2 KSZ8041NL/RNL Description MII / RMII, Commercial Temperature MII / RMII, Industrial Temperature MII / RMII, Automotive Qualified Device KSZ8041NL AM with MII support only. KSZ8041NL AM with RMII support only. RMII with 50MHz clock output, Commercial Temperature RMII with 50MHz clock output, Industrial Temperature M9999-090910-1.4 ...
Page 3
... Added chip maximum current consumption. 1.3 12/11/09 Added Automotive Qualified part number, KSZ8041NL EAM, to Ordering Information. Changed MDIO hold time (min) from 10ns to 4ns. Added LED drive current. Renamed Register 3h bits [3:0] to “manufacturer’s revision number” and changed default value to “ ...
Page 4
... Transmit ........................................................................................................................................................... 20 10Base-T Receive ............................................................................................................................................................ 21 SQE and Jabber Function (10Base-T only)...................................................................................................................... 21 Auto-Negotiation ............................................................................................................................................................... 21 MII Management (MIIM) Interface .................................................................................................................................... 23 Interrupt (INTRP) .............................................................................................................................................................. 23 MII Data Interface (KSZ8041NL only) .............................................................................................................................. 23 MII Signal Definition (KSZ8041NL only) ........................................................................................................................... 24 Transmit Clock (TXC) ................................................................................................................................................... 24 Transmit Enable (TXEN) .............................................................................................................................................. 24 Transmit Data [3:0] (TXD[3:0]) ..................................................................................................................................... 24 Receive Clock (RXC).................................................................................................................................................... 24 Receive Data Valid (RXDV).......................................................................................................................................... 25 Receive Data [3:0] (RXD[3:0]) ...
Page 5
... Electrical Characteristics ................................................................................................................................................ 40 (4) Electrical Characteristics (continued)............................................................................................................................ 41 Timing Diagrams ................................................................................................................................................................. 42 MII SQE Timing (10Base-T) ............................................................................................................................................. 42 MII Transmit Timing (10Base-T) ....................................................................................................................................... 43 MII Receive Timing (10Base-T) ........................................................................................................................................ 44 MII Transmit Timing (100Base-TX) .................................................................................................................................. 45 MII Receive Timing (100Base-TX) ................................................................................................................................... 46 RMII Timing....................................................................................................................................................................... 47 Auto-Negotiation Timing ................................................................................................................................................... 48 MDC/MDIO Timing ........................................................................................................................................................... 49 Reset Timing..................................................................................................................................................................... 50 September 2010 5 KSZ8041NL/RNL M9999-090910-1.4 ...
Page 6
... Micrel, Inc. Reset Circuit ........................................................................................................................................................................ 51 Reference Circuits for LED Strapping Pins...................................................................................................................... 52 Selection of Isolation Transformer.................................................................................................................................... S election of Reference Crystal .......................................................................................................................................... ackage Information........................................................................................................................................................... September 2010 6 KSZ8041NL/RNL M9999-090910-1.4 ...
Page 7
... Figure 4. Typical Straight Cable Connection ....................................................................................................................... 29 Figure 5. Typical Crossover Cable Connection ................................................................................................................... 29 Figure 6. 25MHz Crystal / Oscillator Reference Clock ........................................................................................................ 30 Figure 7. 50MHz Oscillator Reference Clock for KSZ8041NL RMII Mode .......................................................................... 30 Figure 8. KSZ8041NL/RNL Power and Ground Connections.............................................................................................. 31 Figure 9. MII SQE Timing (10Base-T) ................................................................................................................................. 42 Figure 10. MII Transmit Timing (10Base-T) ......................................................................................................................... 43 Figure 11 ...
Page 8
... Table 9. MII Receive Timing (10Base-T) Parameters ......................................................................................................... 44 Table 10. MII Transmit Timing (100Base-TX) Parameters .................................................................................................. 45 Table 11. MII Receive Timing (100Base-TX) Parameters ................................................................................................... 46 Table 12. RMII Timing Parameters – KSZ8041NL .............................................................................................................. 47 Table 13. RMII Timing Parameters – KSZ8041RNL............................................................................................................ 47 Table 14. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ............................................................................... 48 Table 15. MDC/MDIO Timing Parameters ........................................................................................................................... 49 Table 16 ...
Page 9
... Micrel, Inc. Pin Configuration – KSZ8041NL September 2010 ® 32-Pin (5mm x 5mm) MLF 9 KSZ8041NL/RNL M9999-090910-1.4 ...
Page 10
... Micrel, Inc. Pin Description – KSZ8041NL Pin Number Pin Name Type 1 GND Gnd 2 VDDPLL_1.8 3 VDDA_3.3 4 RX- I/O 5 RX+ I/O 6 TX- I/O 7 TX+ I REFCLK 10 REXT I/O 11 MDIO I/O 12 MDC 13 RXD3 / Ipu/O PHYAD0 14 RXD2 / Ipd/O PHYAD1 15 RXD1 / Ipd/O RXD[1] / PHYAD2 16 RXD0 / Ipu/O RXD[0] / ...
Page 11
... Micrel, Inc. Pin Description – KSZ8041NL (Continued) Pin Number Pin Name Type 20 RXER / Ipd/O RX_ER / ISO 21 INTRP Opu 22 TXC 23 TXEN / TX_EN 24 TXD0 / TXD[0] 25 TXD1 / TXD[1] 26 TXD2 27 TXD3 28 COL / Ipd/O CONFIG0 29 CRS / Ipd/O CONFIG1 September 2010 (1) Pin Function MII Mode: Receive Error Output / ...
Page 12
... Micrel, Inc. Pin Description – KSZ8041NL (Continued) Pin Number Pin Name Type 30 LED0 / Ipu/O NWAYEN September 2010 (1) Pin Function LED Output: Programmable LED0 Output / Config Mode: Latched as Auto-Negotiation Enable (register 0h, bit 12) during power-up / reset. See “Strapping Options” section for details. ...
Page 13
... Micrel, Inc. Pin Description – KSZ8041NL (Continued) Pin Number Pin Name Type 31 LED1 / Ipu/O SPEED 32 RST# I PADDLE GND Gnd Notes Power supply. Gnd = Ground Input Output. I/O = Bi-directional. Ipd = Input with internal pull-down (40K +/-30%). Ipu = Input with internal pull-up (40K +/-30%). ...
Page 14
... Micrel, Inc. Strapping Options – KSZ8041NL Pin Number Pin Name Type 15 PHYAD2 Ipd/O 14 PHYAD1 Ipd/O PHYAD0 Ipu CONFIG2 Ipd/O 29 CONFIG1 Ipd/O 28 CONFIG0 Ipd/O 20 ISO Ipd/O 31 SPEED Ipu/O 16 DUPLEX Ipu/O 30 NWAYEN Ipu/O Note: 1. Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise. ...
Page 15
... Micrel, Inc. Pin Configuration – KSZ8041RNL September 2010 ® 32-Pin (5mm x 5mm) MLF 15 KSZ8041NL/RNL M9999-090910-1.4 ...
Page 16
... Interrupt Output: Programmable Interrupt Output Register 1Bh is the Interrupt Control/Status Register for programming the interrupt conditions and reading the interrupt status. Register 1Fh bit 9 sets the interrupt output to active low (default) or active high connect I RMII Transmit Enable Input 16 KSZ8041NL/RNL (2) / (2) / M9999-090910-1.4 ...
Page 17
... The LED0 pin is programmable via register 1Eh bits [15:14], and is defined as follows. LED mode = [00] Link/Activity Pin State No Link H Link L Activity Toggle LED mode = [01] Link Pin State No Link H Link L LED mode = [10] , [11] 17 KSZ8041NL/RNL LED Definition OFF ON Blinking LED Definition OFF ON Reserved M9999-090910-1.4 ...
Page 18
... The LED1 pin is programmable via register 1Eh bits [15:14], and is defined as follows. LED mode = [00] Speed Pin State 10BT H 100BT L LED mode = [01] Activity Pin State No Activity H Activity Toggle LED mode = [10], [11] I Chip Reset (active low) Ground 18 KSZ8041NL/RNL LED Definition OFF ON LED Definition OFF Blinking Reserved M9999-090910-1.4 ...
Page 19
... Pull-down = Full Duplex During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex Mode. Ipu/O Nway Auto-Negotiation Enable Pull-up (default) = Enable Auto-Negotiation Pull-down = Disable Auto-Negotiation During power-up / reset, this pin value is latched into register 0h bit 12. 19 KSZ8041NL/RNL M9999-090910-1.4 ...
Page 20
... The KSZ8041RNL is an enhanced RMII version of the KSZ8041NL that does not require a 50MHz system clock. It uses a 25MHz crystal for its input reference clock and outputs a 50MHz RMII reference clock to the MAC. ...
Page 21
... Priority 4: 10Base-T, half-duplex If auto-negotiation is not supported or the KSZ8041NL/RNL link partner is forced to bypass auto-negotiation, the KSZ8041NL/RNL sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the KSZ8041NL/RNL to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol ...
Page 22
... Force Link Setting Yes Bypass Auto Negotiation and Set Link Mode September 2010 N Parallel Operation o Attempt Auto Listen for 100BASE-TX Negotiation Idles Join Flow Link Mode Set ? Yes Link Mode Set Figure 1. Auto-Negotiation Flow Chart 22 KSZ8041NL/RNL Listen for 10BASE-T Link Pulses No M9999-090910-1.4 ...
Page 23
... INTRP (pin 21 optional interrupt signal that is used to inform the external controller that there has been a status update to the KSZ8041NL/RNL PHY register. Bits[15:8] of register 1Bh are the interrupt control bits, and are used to enable and disable the conditions for asserting the INTRP signal. Bits[7:0] of register 1Bh are the interrupt status bits, and are used to indicate which interrupt conditions have occurred ...
Page 24
... Micrel, Inc. MII Signal Definition (KSZ8041NL only) The Table 2 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information. Direction MII (with respect to PHY, Signal Name KSZ8041NL signal) TXC Output TXEN Input TXD[3:0] Input RXC Output RXDV ...
Page 25
... Provides independent 2-bit wide (di-bit) transmit and receive data paths. • Contains two distinct groups of signals: one for transmission and the other for reception. The KSZ8041NL is configured in RMII mode after it is power-up or reset with the following: • A 50MHz reference clock connected to REFCLK (pin 9). ...
Page 26
... Micrel, Inc. RMII Signal Definition The Tables 3 and 4 describe the RMII signals for KSZ8041NL and KSZ8041RNL. Refer to RMII Specification for detailed information. Direction RMII (with respect to PHY, Signal Name KSZ8041NL signal) REF_CLK Input TX_EN Input TXD[1:0] Input CRS_DV Output RXD[1:0] Output ...
Page 27
... RX_ER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on the MAC. Collision Detection The MAC regenerates the COL signal of the MII from TX_EN and CRS_DV. RMII Signal Diagram The KSZ8041NL RMII pin connections to the MAC are shown in Figure 2. September 2010 Figure 2. KSZ8041NL RMII Interface 27 KSZ8041NL/RNL ...
Page 28
... HP Auto MDI/MDI-X configuration eliminates the confusion of whether to use a straight cable or a crossover cable between the KSZ8041NL/RNL and its link partner. This feature allows the KSZ8041NL/RNL to use either type of cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive pairs from the link partner, and then assigns transmit and receive pairs of the KSZ8041NL/RNL accordingly ...
Page 29
... Modular Connector (RJ-45) HUB (Repeater or Switch) Figure 5. Typical Crossover Cable Connection 29 10/100 Ethernet Media Dependent Interface 1 Receive Pair Transmit Pair Modular Connector (RJ-45) HUB (Repeater or Switch) 10/100 Ethernet Media Dependent Interface 1 Receive Pair Transmit Pair Modular Connector (RJ-45) HUB (Repeater or Switch) KSZ8041NL/RNL M9999-090910-1.4 ...
Page 30
... Power saving mode is disabled by writing a zero to register 1F bit 10. Power Down Mode This mode is used to power down the entire KSZ8041NL/RNL device when it is not in use. Power down mode is enabled by writing a one to register 0 bit 11. In the power down state, the KSZ8041NL/RNL disables all internal functions, except for the MII management interface ...
Page 31
... Micrel, Inc. Reference Circuit for Power and Ground Connections The KSZ8041NL/RNL is a single 3.3V supply device with a built-in 1.8V low noise regulator. The power and ground connections are shown in Figure 8 and Table 6. Ferrite Bead 22uF 3.3V 22uF Figure 8. KSZ8041NL/RNL Power and Ground Connections Power Pin VDDPLL_1 ...
Page 32
... If enabled, auto-negotiation result overrides settings in register 0.13 and 0.8. 0.11 Power Down 1 = Power down mode 0 = Normal operation 0.10 Isolate 1 = Electrical isolation of PHY from MII and 0 = Normal operation September 2010 TX+/TX- 32 KSZ8041NL/RNL (1) Default Mode RW/ Set by SPEED strapping pin. See “Strapping Options” section for details. RW Set by NWAYEN strapping pin. See “ ...
Page 33
... Link is down 1.1 Jabber Detect 1 = Jabber detected 0 = Jabber not detected (default is low) 1.0 Extended 1 = Supports extended capabilities registers Capability September 2010 (1) Default Mode RW/ Inverse of DUPLEX strapping pin value. See “Strapping Options” section for details 000_000 0000 RO/ RO/LL 0 RO/ KSZ8041NL/RNL M9999-090910-1.4 ...
Page 34
... Selector Field [00001] = IEEE 802.3 September 2010 (1) Default Mode RO 0022h RO 0001_01 RO 01_0001 RO Indicates silicon revision Set by SPEED strapping pin. See “Strapping Options” section for details. RW Set by SPEED strapping pin. See “Strapping Options” section for details 0_0001 34 KSZ8041NL/RNL M9999-090910-1.4 ...
Page 35
... Local device does not have next page 6.1 Page Received 1 = New page received 0 = New page not received yet 6.0 Link Partner 1 = Link partner has auto-negotiation capability Auto Link partner does not have auto-negotiation Negotiation Able September 2010 capability capability capability 35 KSZ8041NL/RNL (1) Default Mode ...
Page 36
... RXER Counter Receive error counter for Symbol Error frames September 2010 word equaled logic one word equal to logic zero word equal to logic one (random latency) frame to MII output for fixed latency sending frame (starting with SFD) to MII output 36 KSZ8041NL/RNL (1) Default Mode ...
Page 37
... Interrupt 1b.2 Link Down 1= Link Down occurred Interrupt 0= Link Down did not occurred 1b.1 Remote Fault 1= Remote Fault occurred Interrupt 0= Remote Fault did not occurred 1b.0 Link Up 1= Link Up occurred Interrupt 0= Link Up did not occurred September 2010 Interrupt 37 KSZ8041NL/RNL (1) Default Mode ...
Page 38
... This bit bypasses the control logic and allow transmitter to send pattern even if there is no link. September 2010 LED1 : Speed LED0 : Link/Activity LED1 : Activity LED0 : Link Transmit on TX+/- (pins 7,6) and Receive on RX+/- (pins 5,4) Transmit on RX+/- (pins 5,4) and Receive on TX+/- (pins 7,6) pair 38 KSZ8041NL/RNL (1) Default Mode ...
Page 39
... Enable SQE 1 = Enable SQE test test 0 = Disable SQE test 1f.0 Disable Data 1 = Disable scrambler Scrambling 0 = Enable scrambler Note Read/Write Read only Self-cleared Latch high Latch low. September 2010 (1) Default Mode 000 KSZ8041NL/RNL M9999-090910-1.4 ...
Page 40
... DDA_3.3 , Commercial)...................................... 0°C to +70° Industrial) .......................................-40°C to +85° Automotive Qualified) .............-40°C to +85°C A Max) ................. 125°C J Max)...................... 150° .........................................34°C ...........................................6°C/W JC Min Typ 53.0 38.0 32.0 4.0 2.0 -10 2 0.65 0.7 KSZ8041NL/RNL Max Units 0 µ µ ...
Page 41
... Specification for packaged product only Current consumption is for the single 3.3V supply KSZ8041NL/RNL device only, and includes the 1.8V supply voltage (V the KSZ8041NL/RNL. The PHY port’s transformer consumes an additional 45mA @ 3.3V for 100Base-TX and 70mA @ 3.3V for 10Base-T. September 2010 (4) ...
Page 42
... September 2010 Figure 9. MII SQE Timing (10Base-T) Description TXC period TXC pulse width low TXC pulse width high COL (SQE) delay after TXEN de-asserted COL (SQE) pulse duration Table 7. MII SQE Timing (10Base-T) Parameters 42 KSZ8041NL/RNL Min Typ Max Unit 400 ns 200 ns 200 ns 2 ...
Page 43
... TXD[3:0] setup to rising edge of TXC TXEN setup to rising edge of TXC TXD[3:0] hold from rising edge of TXC TXEN hold from rising edge of TXC TXEN high to CRS asserted latency TXEN low to CRS de-asserted latency Table 8. MII Transmit Timing (10Base-T) Parameters 43 KSZ8041NL/RNL Min Typ Max Unit 400 ns 200 ...
Page 44
... Figure 11. MII Receive Timing (10Base-T) Description RXC period RXC pulse width low RXC pulse width high (RXD[3:0], RXER, RXDV) output delay from rising edge of RXC CRS to (RXD[3:0], RXER, RXDV) latency Table 9. MII Receive Timing (10Base-T) Parameters 44 KSZ8041NL/RNL Min Typ Max Unit 400 ns 200 ns 200 ns ...
Page 45
... TXD[3:0] setup to rising edge of TXC TXEN setup to rising edge of TXC TXD[3:0] hold from rising edge of TXC TXEN hold from rising edge of TXC TXEN high to CRS asserted latency TXEN low to CRS de-asserted latency Table 10. MII Transmit Timing (100Base-TX) Parameters 45 KSZ8041NL/RNL Min Typ Max Unit ...
Page 46
... Figure 13. MII Receive Timing (100Base-TX) Description RXC period RXC pulse width low RXC pulse width high (RXD[3:0], RXER, RXDV) output delay from rising edge of RXC CRS to RXDV latency CRS to RXD[3:0] latency CRS to RXER latency Table 11. MII Receive Timing (100Base-TX) Parameters 46 KSZ8041NL/RNL Min Typ Max Unit ...
Page 47
... Figure 14. RMII Timing – Data Received from RMII Figure 15. RMII Timing – Data Input to RMII Description Min Clock cycle Setup time 4 Hold time 2 Output delay 3 Table 12. RMII Timing Parameters – KSZ8041NL Description Min Clock cycle Setup time 4 Hold time 1 Output delay 9 Table 13. RMII Timing Parameters – KSZ8041RNL ...
Page 48
... Table 14. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters September 2010 Figure 16. Auto-Negotiation Fast Link Pulse (FLP) Timing Description FLP Burst to FLP Burst FLP Burst width Clock/Data Pulse width Clock Pulse to Data Pulse Clock Pulse to Clock Pulse Number of Clock/Data Pulse per FLP Burst 48 KSZ8041NL/RNL Min Typ Max Units 100 ns 55 ...
Page 49
... MDIO (PHY input) setup to rising edge of MDC 1MD1 t MDIO (PHY input) hold from rising edge of MDC MD2 t MDIO (PHY output) delay from rising edge of MDC MD3 September 2010 Figure 17. MDC/MDIO Timing Table 15. MDC/MDIO Timing Parameters 49 KSZ8041NL/RNL Min Typ Max Unit 400 222 ns M9999-090910-1 ...
Page 50
... Micrel, Inc. Reset Timing The KSZ8041NL/RNL reset timing requirement is summarized in the following figure and table. Parameter After the de-assertion of reset recommended to wait a minimum of 100 us before starting programming on the MIIM (MDC/MDIO) Interface. September 2010 Figure 18. Reset Timing Description Stable supply voltage to reset high ...
Page 51
... Micrel, Inc. Reset Circuit The reset circuit in Figure 19 is recommended for powering up the KSZ8041NL/RNL if reset is triggered by the power supply. The reset circuit in Figure 20 is recommended for applications where reset is driven by another device (e.g., CPU or FPGA). At power-on-reset and D1 provide the necessary ramp rise time to reset the KSZ8041NL/RNL device. The RST_OUT_n from CPU/FPGA provides the warm reset after power up ...
Page 52
... The Figure 21 shows the reference circuits for pull-up, float and pull-down on the LED1 and LED0 strapping pins. September 2010 Pull-up KSZ8041NL/RNL LED pin Float KSZ8041NL/RNL LED pin Pull-down KSZ8041NL/RNL LED pin Figure 21. Reference Circuits for LED Strapping Pins 52 KSZ8041NL/RNL 3.3V 3.3V 3.3V M9999-090910-1.4 ...
Page 53
... LF8505 Yes LF-H41S Yes H1102 Yes H1260 Yes HB726 Yes TLA-6T718 Yes Table 18. Qualified Single Port Magnetics Value 25 ± Table 19. Typical Reference Crystal Characteristics 53 KSZ8041NL/RNL Test Condition 100mV, 100kHz, 8mA 1MHz (min.) 0MHz – 65MHz Number of Port Units MHz ppm pF Ω ...
Page 54
... A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to September 2010 32-Pin (5mm x 5mm) MLF® Package fully indemnify Micrel for any damages resulting from such use or sale. © 2006 Micrel, Incorporated. 54 KSZ8041NL/RNL http://www.micrel.com M9999-090910-1.4 ...