CY7C9689A-AI Cypress Semiconductor Corp, CY7C9689A-AI Datasheet - Page 15

• Manufacturer Part Number: CY7C9689A-AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9689A-AI

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02020 Rev. *D
Synchronous Interface
Synchronous interface clocking operates the entire transmit
data path synchronous to REFCLK. It is enabled by
connecting FIFOBYP LOW to disable the internal FIFOs.
Asynchronous Interface
Asynchronous interface clocking controls the writing of host
bus data into the Transmit FIFO. It is enabled by setting
FIFOBYP HIGH to enable the internal FIFOs. In these config-
urations, all writes to the Transmit Input Register, and
associated transfers to the Transmit FIFO, are controlled by
TXCLK. The remainder of the transmit data path is clocked by
REFCLK or synthesized derivatives of REFCLK.
Shared Bus Timing Model
The Shared Bus Timing Model allows multiple CY7C9689A
transmitters to be accessed from a common host bus. It is
enabled by setting EXTFIFO LOW. In shared bus timing, the
TXEMPTY and TXFULL outputs and TXEN input are all active
LOW signals. If the CY7C9689A is addressed by asserting CE
LOW, it becomes “selected” when TXEN is asserted LOW.
Following selection, data or command is written into the
Transmit FIFO on every clock cycle where TXEN remains
LOW.
Cascade Timing Model
The Cascade timing model is a variation of the shared bus
timing model. Here the TXEMPTY and TXFULL outputs, and
TXEN input, are all active HIGH signals. Cascade timing
makes use of the same selection sequences as shared bus
timing, but write data accesses use a delayed write. This
delayed write is necessary to allow direct coupling to external
FIFOs, or to state machines that initiate a write operation one
clock cycle before the data is available on the bus.
Cascade timing is enabled by setting EXTFIFO HIGH.
When used for FIFO depth expansion, Cascade timing allows
the size of the internal Transmit FIFO to be expanded to an
almost unlimited depth. It allows a CY7C42x5 series
synchronous FIFO to be attached to the transmit interface
without any extra logic, as shown in
FF*
WEN*
D
TXCLK
Figure 3. External FIFO Depth Expansion of the
CY7C9689A Transmit Data Path
CY7C42x5 FIFO
WCLK
FF*
WEN*
D
RCLK
REN*
EF*
Q
Figure 3
“1”
CY7C9689A
EXTFIFO
TXEN
TXFULL
TXCLK
TXDATA
TXSC/D
Transmit FIFO
The Transmit FIFO is used to buffer data and command
captured in the input register for later processing and trans-
mission. This FIFO is sized to hold 256 14-bit characters.
When the Transmit FIFO is enabled, and a Transmit FIFO
write is enabled (the device is selected and TXEN is sampled
asserted), data is captured in the transmit input register and
stored into the Transmit FIFO. All Transmit FIFO write opera-
tions are clocked by TXCLK.
The Transmit FIFO presents Full, Half-Full, and Empty FIFO
flags. These flags are provided synchronous to TXCLK. When
the Transmit FIFO is enabled, it allows operation with a
Moore-type external controlling state machine. When
configured for Cascade timing, the timing and active levels of
these signals are also designed to support direct expansion to
Cypress CY7C42x5 synchronous FIFOs.
Regardless of bus width (8- or 10-bit characters) the Transmit
FIFO can be clocked at any rate from DC to 50 MHz. This
gives the Transmit FIFO a maximum bandwidth of 50 million
characters per second. Since the serial outputs can only move
20 million characters per second at their fastest operating rate,
there is ample time to service multiple CY7C9689A HOTLinks
with a single controller.
The read port of the Transmit FIFO is connected to a logic
block that performs data formatting and validation. All data
read operations from the Transmit FIFO are controlled by a
Transmit Control State Machine that operates synchronous to
REFCLK.
Encoder Block
The Encoder logic block performs two primary functions:
encoding the data for serial transmission and generating BIST
patterns to allow at-speed link and device testing.
BIST LFSR
The Encoder logic block operates on data stored in a register.
This register accepts information directly from the Transmit
FIFO, the Transmit Input Register or from the Transmit Control
State Machine when it inserts special characters into the data
stream.
This same register is converted into a Linear Feedback Shift
Register (LFSR) when the BIST pattern generator is enabled
(TXBISTEN is LOW). When enabled, this LFSR generates a
511-character sequence that includes all Data and Special
Character codes, including the explicit violation symbols. This
provides a predictable but pseudo-random sequence that can
be matched to an identical LFSR in the Receiver.
Encoder
The data passed through the Transmit FIFO and pipeline
register, or as received directly from the Transmit Input
Register, is seldom in a form suitable for transmission across
a serial link. The characters must usually be processed or
transformed to guarantee:
•a minimum transition density (to allow the serial receiver PLL
•some way to allow the remote receiver to determine the
to extract a clock from the data stream)
correct character boundaries (framing).
CY7C9689A
Page 15 of 51
[+] Feedback