CYP15G0402DXB-BGI Cypress Semiconductor Corp, CYP15G0402DXB-BGI Datasheet - Page 23

CYP15G0402DXB-BGI

Manufacturer Part Number
CYP15G0402DXB-BGI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CYP15G0402DXB-BGI

Lead Free Status / RoHS Status
Not Compliant
Document #: 38-02057 Rev. *G
CYP(V)15G0402DXB REFCLK Switching Characteristics Over the Operating Range (continued)
CYP(V)15G0402DXB Transmit Serial Outputs and TX PLL Characteristics Over the Operating Range
CYP(V)15G0402DXB Receive Serial Inputs and CDR PLL Characteristics Over the Operating Range
Capacitance
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
C
C
Notes:
29. The duty cycle specification is a simultaneous condition with the t
30. While sending continuous K28.5s, outputs loaded to a balanced 100Ω load, measured at the cross point of differential outputs, over the operating range.
31. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the operating
32. Total jitter is calculated at an assumed BER of 1E −12. Hence: total jitter (t
33. Receiver UI (Unit Interval) is calculated as 1 / (f
REFD
REFR
REFF
TREFDS
TREFDH
REFRX
B
RISE
FALL
DJ
RJ
TXLOCK
RXLOCK
RXUNLOCK
JTOL
DJTOL
INTTL
INPECL
[25, 30, 32]
[25, 31, 32]
cannot be as large as 30% – 70%.
range.
(when RXRATE = HIGH) or 1 / (f
Parameter
[25]
[25]
Parameter
[25, 26, 27]
[29]
[25, 26, 27]
Parameter
[8]
[25]
Bit Time
CML Output Rise Time 20% – 80% (CML Test
Load)
CML Output Fall Time 80% – 20% (CML Test Load) SPDSEL = HIGH
Deterministic Jitter (peak-peak)
Random Jitter (
Transmit PLL lock to REFCLK
TTL Input Capacitance
PECL input Capacitance
REFCLK Duty Cycle
REFCLK Rise Time (20% – 80%)
REFCLK Fall Time (20% – 80%)
Transmit Data Setup Time to REFCLK (TXCKSEL = LOW)
Transmit Data Hold Time from REFCLK (TXCKSEL = LOW)
REFCLK Frequency Referenced to Received Clock Period
Receive PLL lock to input data stream (cold start)
Receive PLL lock to input data stream
Receive PLL Unlock Rate
Total Jitter Tolerance
Deterministic Jitter Tolerance
REF
* 10) (when RXRATE = LOW) of the remote transmitter if data is being received. In an operating link this is equivalent to t
Description
σ
)
REF
Description
* 20) (when RXRATE = HIGH) or 1 / (f
Description
REFH
T
T
A
A
and t
= 25°C, f
= 25°C, f
J
REFL
) = (t
parameters. This means that at faster character rates the REFCLK duty cycle
RJ
REF
0
0
* 14) + t
Test Conditions
= 1 MHz, V
= 1 MHz, V
* 10) (when RXRATE = LOW) if no data is being received, or 1 / (f
SPDSEL = HIGH
SPDSEL = LOW
SPDSEL = LOW
SPDSEL = MID
SPDSEL = MID
DJ
IEEE 802.3z
IEEE 802.3z
IEEE 802.3z
IEEE 802.3z
.
Condition
CC
CC
= 3.3V
= 3.3V
-1500
5100
Min.
Min.
100
180
100
180
1.7
0.8
600
370
50
50
30
CYP15G0402DXB
CYV15G0402DXB
Max.
7
4
+1500
Max.
1000
1000
Max.
376K
376K
660
270
500
270
500
200
70
25
11
2
2
46
Page 23 of 29
Unit
pF
pF
UI
Unit
ppm
REF
Unit
ns
ns
ns
ns
%
ps
ps
ps
ps
ps
ps
ps
ps
ps
us
UI
UI
ps
ps
[33]
* 20)
B
.
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