AM79C031JC AMD (ADVANCED MICRO DEVICES), AM79C031JC Datasheet - Page 18

• Manufacturer Part Number: AM79C031JC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C031JC

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Master Clock
For 2.048 MHz ±100 ppm or 4.096 MHz ±100 ppm operation:
Notes:
1. DCLK may be stopped in the High or Low state indefinitely without loss of information. If CS makes a transition to the Low
2. The PCM clock (PCLK) frequency must be an integer multiple of the frame sync (FS) frequency and synchronous to the MCLK
3. TSC is delayed from FS by a typical value of N
4. There is a special conflict detection circuitry that prevents high-power dissipation from occurring when the DXA or DXB pins
5. The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs last.
6. t
7. The DSLAC device requires 40 cycles of the 8 MHz internal clock (5 µs) between SIO operations. If the MPI is being accessed
SWITCHING WAVEFORMS
Input and Output Waveforms for AC Tests
Master Clock Timing
18
No.
35
36
37
38
39
state, the last byte received is interpreted by the Microprocessor Interface logic.
frequency. The actual PCLK rate is dependent on the number of channels allocated within a frame. The DSLAC supports 2–
128 channels. A PCLK of 1.544 MHz can be used for standard US transmission systems. The minimum clock frequency is
128 kHz.
of two DSLAC devices are tied together and one DSLAC device starts to transmit before the other has gone into a high-
impedance state.
while the MCLK input is not active, a Chip Select Off time of 20 µs is required.
TSO
is defined as the time at which the output achieves the open circuit condition.
Symbol
t
t
t
t
t
MCY
MCR
MCF
MCH
MCL
Master Clock Period (2.048 MHz)
Master Clock Period (4.096 MHz)
Rise Time of Clock
Fall Time of Clock
MCLK High Pulse Width (2.048 MHz)
MCLK High Pulse Width (4.096 MHz)
MCLK Low Pulse Width (2.048 MHz)
MCLK Low Pulse Width (4.096 MHz)
0.45
2.4
V
IL
38
Parameter
V
Am79C02/03/031(A) Data Sheet
IH
2.0
0.8
39
37
•
t
PCY
, where N is the value stored in the time/clock-slot register.
Points
Test
35
2.0
0.8
488.23
244.11
Min
200
200
80
80
36
488.28
244.14
Typ
15
488.33
244.17
Max
15
09875H-012
09875H-013
Units
ns