XC3S50A-4TQG144I Xilinx Inc, XC3S50A-4TQG144I Datasheet - Page 2

• Manufacturer Part Number: XC3S50A-4TQG144I
• Description: FPGA, SPARTAN-3A, 50K, 144TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Ar

Specifications of XC3S50A-4TQG144I

• No. Of Logic Blocks: 176
• No. Of Gates: 50000
• No. Of Macrocells: 1584
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• Total Ram Bits: 55296
• No. Of I/o's: 108
• Clock Management: DCM
• I/o Supply: RoHS Compliant
• Number Of Logic Elements/cells: 1584
• Number Of Labs/clbs: 176
• Number Of I /o: 108
• Number Of Gates: 50000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1589; XC3S50A-4TQG144I

Industry’s first 90nm FPGA Electronic Serial Numbering
Each FPGA includes a permanent unique Device DNA serial number that can be used to
safeguard both hardware and software IP. It is ideal for tracking production serial numbers,
product registrations and system ID. Customers have complete flexibility in implementing
custom algorithms for the security solutions that can significantly deter reverse-engineering,
cloning and overbuilding.
Widest Support for I/O Standards
The Spartan-3A FPGA is especially suitable for display devices supporting both TMDS and
PPDS standards. With support for 26 popular single-ended and differential signaling stan-
dards including TMDS, PPDS, SSTL3 Class I & II, full hot-swap compliance, and pre-engi-
neered interface IP solutions such as PCI, PCI Express, USB, Firewire, CAN, SPI, I2C, etc, the
Spartan-3A platform provides an industry-leading connectivity solution.
Comprehensive Configuration Capabilities
The Spartan-3A platform features enhanced Multi-Boot capability with watchdog timer for
guaranteed “golden” configuration. This enables intelligent recovery from configuration
errors and improves field upgradeability.
Flexible Power-Management Modes
A new Suspend mode provides a very flexible and effective way to preserve power. In this
mode, the power is comparable to quiescent current, and the configuration data as well as
flip-flop and RAM values are maintained. It also includes a fast wake-up mechanism and sys-
tem level synchronization across time domains.
Dynamic Input Delay
Selecting delay-length for both registered and combinatorial inputs allows for precise timing
relationship adjustment between clock and data. Combinatorial input delay can now also be
dynamically changed through the interconnect. Source synchronous designs will significantly
benefit from this feature.
Take the Next Step
Visit our website www.xilinx.com/spartan3a or call your local sale office or distributor for
more information about Spartan-3A FPGAs. To start your design immediately, download
your free ISE WebPACK
FPGAs, order your hardware development board at www.xilinx.com/s3astarter
Device
System Gates
Logic Cells
Dedicated Multipliers
Block RAM Blocks
Block RAM Bits
Distributed RAM Bits
DCMs
I/O Standards
Max Differential I/O
Max Single Ended I/O
Device
TQ144 20 x 20 mm
FT256 17 x 17 mm
FG320 19 x 19 mm
FG400 21 x 21 mm
FG484 23 x 23 mm
FG676 27 x 27 mm
TM
design tools at www.xilinx.com/ise. To begin evaluating Spartan-3A
Spartan-3A FPGA Platform
XC3S50A
50K
1,584
3
3
54K
11K
2
26
64
144
Package and I/O Offerings
XC3S50A
108
144
XC3S200A
200K
4,032
16
16
288K
28K
4
26
112
248
XC3S200A
195
248
XC3S400A
400K
8,064
20
20
360K
56K
4
26
142
311
XC3S400A
195
251
311
XC3S700A
700K
13,248
20
20
360K
92K
8
26
165
372
XC3S700A
311
372
XC3S1400A
1400K
25,344
32
32
576K
176K
8
26
227
502
XC3S1400A
375
502
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Printed in U.S.A. PN 2010
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