XC5VLX30-1FFG324C Xilinx Inc, XC5VLX30-1FFG324C Datasheet - Page 70

FPGA, VIRTEX-5 LX, 30K, 324FBGA

XC5VLX30-1FFG324C

Manufacturer Part Number
XC5VLX30-1FFG324C
Description
FPGA, VIRTEX-5 LX, 30K, 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr

Specifications of XC5VLX30-1FFG324C

No. Of Logic Blocks
4800
Family Type
Virtex-5
No. Of Speed Grades
1
Total Ram Bits
1179648
No. Of I/o's
220
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
Core Supply Voltage Range
1V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1558

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VLX30-1FFG324C
Manufacturer:
XILINX
Quantity:
128
Part Number:
XC5VLX30-1FFG324C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX30-1FFG324C
Manufacturer:
XILINX
0
Part Number:
XC5VLX30-1FFG324CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 91: Global Clock Setup and Hold Without DCM or PLL (Cont’d)
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
T
PSFD
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
IFF = Input Flip-Flop or Latch
A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0"
is listed, there is no positive hold time.
Symbol
/ T
PHFD
Full Delay (Legacy Delay or Default Delay)
Global Clock and IFF
Description
(2)
without DCM or PLL
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
XC5VTX150T
XC5VTX240T
XC5VFX30T
XC5VFX70T
XC5VFX100T
XC5VFX130T
XC5VFX200T
Device
–0.27
–0.30
–0.42
–0.55
2.05
1.85
2.20
2.33
N/A
N/A
N/A
-3
Speed Grade
–0.82
–0.85
–0.27
–0.30
–0.42
–0.54
–0.43
2.35
2.59
2.25
2.06
2.38
2.59
2.52
-2
–0.82
–0.85
–0.27
–0.30
–0.42
–0.54
–0.43
2.59
2.87
2.57
2.35
2.66
2.95
2.81
-1
Units
ns
ns
ns
ns
ns
ns
ns
70

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