AD7476ABRM-REEL Analog Devices Inc, AD7476ABRM-REEL Datasheet - Page 17

• Manufacturer Part Number: AD7476ABRM-REEL
• Description: IC,A/D CONVERTER,SINGLE,12-BIT,CMOS,TSSOP,8PIN
• Manufacturer: Analog Devices Inc

Specifications of AD7476ABRM-REEL

• Rohs Status: RoHS non-compliant
• Design Resources: Output Channel Monitoring Using AD5380 (CN0008) AD5382 Channel Monitor Function (CN0012) AD5381 Channel Monitor Function (CN0013) AD5383 Channel Monitor Function (CN0015) AD5390/91/92 Channel Monitor Function (CN0030) Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 17.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• For Use With: EVAL-AD7476ACBZ - BOARD EVALUATION FOR AD7476AAD7476-DBRD - BOARD EVAL FOR AD7476AD7476A-DBRD - BOARD EVAL FOR AD7476A

Table 8 provides typical performance data with various op amps
used as the input buffer for a 100 kHz input tone at room
temperature under the same setup conditions.
Table 8. AD7476A Typical Performance with Various Input
Buffers, V
Op Amp in the Input Buffer
AD711
AD797
AD845
When no amplifier is used to drive the analog input, limit the
source impedance to low values. The maximum source imped-
ance depends on the amount of total harmonic distortion (THD)
that can be tolerated. The THD increases as the source impedance
increases, degrading the performance (see Figure 13).
DD
= 3 V
AD7476A SNR Performance (dB)
72.3
72.5
71.4
Rev. F | Page 17 of 28
DIGITAL INPUTS
The digital inputs applied to the AD7476A/AD7477A/AD7478A
are not limited by the maximum ratings that limit the analog
input. Instead, the digital inputs applied can reach 7 V and are
not restricted by the V
For example, if operating the AD7476A/AD7477A/AD7478A
with a V
However, note that the data output on SDATA still has 3 V logic
levels when V
being restricted by the V
sequencing issues are avoided. If CS or SCLK are applied before
V
input if a signal greater than 0.3 V were applied prior to V
DD
, there is no risk of latch-up as there would be on the analog
DD
of 3 V, use 5 V logic levels on the digital inputs.
DD
= 3 V. Another advantage of SCLK and CS not
AD7476A/AD7477A/AD7478A
DD
DD
+ 0.3 V limit as on the analog input.
+ 0.3 V limit is that power supply
DD
.