MIC2185YM Micrel Inc, MIC2185YM Datasheet - Page 12

• Manufacturer Part Number: MIC2185YM
• Description: SO-16 Low Vin Synchronous Buck PWM Control IC ( )
• Manufacturer: Micrel Inc

Specifications of MIC2185YM

• Duty Cycle: 95%
• Lead Free Status: Lead free
• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 440kHz
• Voltage - Supply: 2.9 V ~ 14 V
• Buck: No
• Boost: Yes
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: 440kHz
• Number Of Pwm Outputs: 1
• On/off Pin: Yes
• Adjustable Output: Yes
• Topology: Boost/Buck
• Switching Freq: 400KHz
• Operating Supply Voltage (max): 14V
• Synchronous Pin: Yes
• Rise Time: 50ns
• Fall Time: 50ns
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: SOIC
• Lead Free Status / RoHS Status: Compliant
• Other names: 576-1714-5; MIC2185YM

Reference, Enable and UVLO Circuits
The output drivers are enabled when the following conditions
are satisfied:
The internal bias circuitry generates a 1.245V bandgap
reference for the voltage error amplifier and a 3V V
age for the internal supply bus. The reference voltage in the
MIC2185 is buffered and brought out to pin 8. The VREF
pin must be bypassed to GND (pin 4) with a 0.1µF capaci-
tor. The VDD pin must be decoupled to ground with a 1µF
ceramic capacitor.
The Enable pin (pin 7) has two threshold levels, allowing the
MIC2185 to shut down in a micro-current mode, or turn off
output switching in standby mode. Below 0.9V (typical), the
device is forced into a low-power shutdown. If the enable pin
is between 0.9V and 1.5V (typical) the output gate drive is
disabled but the internal circuitry is powered on and the soft
start pin voltage is forced low. There is typically 140mV of
hysteresis below the 1.5V threshold to insure the part does
not oscillate on and off due to ripple voltage on the input.
Raising the Enable voltage above the UVLO threshold of 1.5V
enables the output drivers and allows the soft start capacitor
to charge. The Enable pin may be pulled up to V
Oscillator & Sync
The internal oscillator is self-contained and requires no
external components. The f/2 pin allows the user to select
from two switching frequencies. A low level sets the oscilla-
tor frequency to 400kHz and a high level sets the oscillator
frequency to 200kHz. The maximum duty cycle for both
frequencies is typically 85%. The minimum pulse width in-
creases but does not double when the frequency is changed
from 400kHz to 200kHz. This means the minimum duty cycle
is slightly lower at 200kHz. This may be important as the
input voltage approaches the output voltage. At lower duty
cycles, the input voltage can be closer to the output voltage
without the output rising out of regulation.
A frequency foldback mode is enabled if the voltage on the
Feedback pin (pin 6) is less than 0.3V. In frequency foldback
the oscillator frequency is reduced by approximately a factor
of 4. For the 400kHz setting, the oscillator runs at 100khz in
frequency foldback. For a 200kHz setting the oscillator runs
at approximately 50kHz.
The SYNC input (pin 11) allows the MIC2185 to synchronize
with an external CMOS or TTL clock signal. The rising edge
of the sync signal generates a reset signal in the oscillator,
which turns off the high side gate drive output. The low side-
drive then turns on, restarting the switching cycle. The sync
signal is inhibited when the controller operates in skip mode
or frequency foldback. The sync signal frequency must be
greater than the maximum specified free running frequency of
the MIC2185. If the synchronizing frequency is lower, double
pulsing of the gate drive outputs will occur. When not used,
the sync pin must be connected to ground.
Figure 8 shows the timing between the external sync signal,
MIC2185
• The VDD voltage (pin 10) is greater than its
• The voltage on the Enable pin is greater than
undervoltage threshold.
the Enable /UVLO threshold.
IN
A.
DD
volt-
12
low side-drive and the high side drive when the f/2 pin is low.
The delay between the rising edge of the sync signal and the
turn on of the low side gate drive is typically 900ns when the
f/2 pin is high and 600ns when the f/2 pin is low.
The maximum recommended output switching frequency is
600kHz. Synchronizing to higher frequencies may be pos-
sible, however there are some concerns. As the switching
frequency is increased, the switching period decreases.
The minimum on time in the MIC2185 becomes a greater
part of the total switching period. This may prevent proper
operation as Vin approaches Vout and may also minimize
the effectiveness of the current limit circuitry. The maximum
duty cycle decreases as the sync frequency is increased.
Figure 9 shows the relationship between the minimum and
maximum duty cycle and frequency.
Table 1 summarizes the differences in the MIC2185 for the
two different states of the f/2 pin.
F/2 pin Switching
Level
(Low Side FE T Drain)
Switch NodeVoltage
0
1
High Side FET
Low Side FET
Gate Drive
Gate Drive
Sync Input
Frequency Max Duty Min. Duty SKIP Mode
2V/div
5V/div
5V/div
5V/div
(kHz)
400
200
Figure 8. Sync Waveforms
100
90
80
70
60
50
40
18
16
14
12
10
8
6
4
2
0
0
MIC2185 Sync Frequency
F /2 HIG H
F /2 HIG H
MIC2185 Table 1
100 200 300 400 500 600
cycle (%) cycle (%)
600ns
Typical
vs. Dut y c y cle
FREQUENCY (kHz)
Figure 9
85
85
Sync Waveform
TIME (500ns/div)
F /2 LOW
Typical
F /2 LOW
6
6
October 2005
t
OFF
1µs
2µs
in