NCP1393BDR2G ON Semiconductor, NCP1393BDR2G Datasheet - Page 10

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NCP1393BDR2G

Manufacturer Part Number
NCP1393BDR2G
Description
HV HALF-BRIDGE DRIVER
Manufacturer
ON Semiconductor
Type
High Side/Low Sider
Series
-r
Datasheet

Specifications of NCP1393BDR2G

Rise Time
40 ns
Fall Time
20 ns
Mounting Style
SMD/SMT
Bridge Type
Half Bridge
Number Of Drivers
2
Number Of Outputs
2
Input Type
Non-Inverting
On-state Resistance
-
Current - Output / Channel
-
Current - Peak Output
1A
Voltage - Supply
16V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NCP1393BDR2G
Manufacturer:
ON/安森美
Quantity:
20 000
which is proportional to the current flowing out from the
Rt pin. The discharging current I
on this capacitor reaches 2.5 V. The output drivers are
disabled during discharge period so the dead time length is
given by the discharge current sink capability. Discharge
sink is disabled when voltage on the timing capacitor
reaches zero and charging cycle starts again. The charging
current and thus also whole oscillator is disabled during the
PFC delay period to keep the IC consumption below 400 mA.
resistor value. This frequency is reached if there is no
optocoupler or current feedback action and soft start period
has been already finished. The maximum switching
frequency excursion is limited by the Rf
that the F
saturation voltage value. Resistor Rf
capacitor C
elapses. The Rt pin is grounded via an internal switch during
the PFC delay period to assure that the soft start capacitor
will be fully discharged via Rfstart resistor.
current control loop) to the Rt pin. The only one limitation
lies in the Rt pin reference voltage which is Vref
Used regulator has to be capable to work with voltage lower
than Vref
The internal timing capacitor Ct is charged by current
The minimum switching frequency is given by the Rt
There is a possibility to connect other control loops (like
Rt
max
.
SS
prepares the soft start period after PFC timer
value is influenced by the optocoupler
R
C
DT
fstart
SS
is applied when voltage
NCP1393
max
start
R
t
Figure 22. Typical Rt Pin Connection
R
t
selection. Note
together with
Rt
= 3.5 V.
http://onsemi.com
R
fmax
Voltage Feedback
10
(to secondary
voltage regulator)
This is valuable for applications that are supplied from
auxiliary winding and V
energy during PFC delay period.
it is necessary to adjust minimum operating frequency with
high accuracy. The designer also needs to limit maximum
operating and startup frequency. All these parameters can be
adjusted using few external components connected to the Rt
pin as depicted in Figure 22.
Figure 22 to prepare current feedback loop. Diode D1 is
used to enable regulator biasing via resistor R
saturation voltage of this solution is 1.25 + 0.6 = 1.85 V for
room temperature. Shottky diode will further decrease
saturation voltage. Rf
maximum frequency that can be pushed by this regulation
loop. This parameter is not temperature stable because of the
D1 temperature drift.
Brown−Out Protection
application from low DC input voltages. Below a given
level, the controller blocks the output pulses, above it, it
authorizes them. The internal circuitry, depicted by
Figure 23, offers a way to observe the high−voltage (HV)
rail.
For the resonant applications and light ballast applications
The TLV431 shunt regulator is used in the example from
The Brown−Out circuitry (BO) offers a way to protect the
R
TLV431
D1
fmax−OCP
Current Feedback
R
comp
max
CC
− OCP resistor value, limits the
(to primary
current sensor)
capacitor is supposed to provide
V
C
CC
comp
R
bias
bias
. Total

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