PIC18F26J13-I/SS Microchip Technology, PIC18F26J13-I/SS Datasheet - Page 413

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PIC18F26J13-I/SS

Manufacturer Part Number
PIC18F26J13-I/SS
Description
28-pin, GP, 64KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SSOP .209i
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18F26J13-I/SS

Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F26J13-I/SS
Manufacturer:
Microchip Technology
Quantity:
135
SUBFSR
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2010 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FSR2
FSR2
Q1
=
=
register ‘f’
Subtract Literal from FSR
SUBFSR f, k
0  k  63
f  [ 0, 1, 2 ]
FSR(f) – k  FSRf
None
The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified by
‘f’.
1
1
SUBFSR 2, 23h
Read
1110
Q2
03FFh
03DCh
1001
Process
Data
Q3
ffkk
destination
Write to
kkkk
Q4
Preliminary
SUBULNK
Syntax:
Operands:
Operation:
Status Affected: None
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
PIC18(L)F2X/4XK22
Before Instruction
After Instruction
Operation
Decode
FSR2
PC
FSR2
PC
Q1
No
Subtract Literal from FSR2 and Return
SUBULNK k
0  k  63
FSR2 – k  FSR2
(TOS) PC
The 6-bit literal ‘k’ is subtracted from the
contents of the FSR2. A RETURN is then
executed by loading the PC with the TOS.
The instruction takes two cycles to
execute; a NOP is performed during the
second cycle.
This may be thought of as a special case of
the SUBFSR instruction, where f = 3 (binary
‘11’); it operates only on FSR2.
1
2
1110
=
=
=
=
register ‘f’
Operation
SUBULNK 23h
Read
Q2
No
03FFh
0100h
03DCh
(TOS)
1001
Operation
Process
Data
Q3
No
DS41412D-page 413
11kk
destination
Operation
Write to
kkkk
Q4
No

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